The MVD ASI receiver core is a drop-in module that includes the following functions :
• Clock/Data recovery
• Serial/parallel Conversion
• Sync Byte (FC Comma Detection)
• 8B/10B decoding
• Auto adaptation to 188/204 bytes packet Input
• 188 bytes MPEG-TS output
No external components required (1)
(1) External equalizer and/or transformer is recommended for long cable interfaces.
ASI Receiver
Overview
Key Features
- Multi mode ASI receiver
- • European standard EN50083-9 Annex B
- • Drop-in module for Virtex-6™, Virtex-5™, Spartan-6™ and Spartan™-3/E/A FPGAs
- • 27MHz Single Clock
- • Supports 188 or 204 bytes packet input
- • Supports direct ASI interface (clock recovery from Data)
- • Supports Data Packet or Data Burst format
- • Single channel – support for multi channel
- • Full synthesizable RTL VHDL design (not delivered) for easy customization
- • Design delivered as Netlist
Benefits
- ASI Receiver may be used in applications related to
- DVB/MPEG-2 transport streams.
Technical Specifications
Availability
Available