The LVDS Receiver IP is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolution and Dual Link transmission between Host and Flat Panel Display with up to UXGA resolution. It converts the LVDS data stream back into 70 bits of CMOS/TTL data with a variety of LCD panel controllers.
SMIC 0.13um LVDS Receiver
Overview
Key Features
- Function compatible with the National DS90CF386
- Converts 4-pair LVDS data stream into parallel 28 bits of CMOS/TTL data
- Converts 8-pair LVDS data stream into parallel 56 bits of CMOS/TTL data with double channel
- Wide dot clock range: 25 ~ 170MHz, suitable for VGA, SVGA, XGA, SXGA, SXGA+ and UXGA
- Supports Dual Link up to 170MHz dot clock for UXGA
- On-chip DLL does not require any external component
- Low-power CMOS design
- Power-down control function
- Compatible with the TIA/EIA-644 LVDS standards
- Full industrial operating temperature range: -40 ~ +85 ¡ãC
- SMIC 0.13um Logic Salicide Process (1p8m, 1.2V/3.3V)
- Off chip 100ohm resistance between the receiver¡¯s positive input and negative input
- Negative clock edge for data output
- More detail, please go to below website to contact VeriSilicon location sales:http://www.verisilicon.com/cn/contactus.asp
Technical Specifications
Foundry, Node
SMIC 0.13um
SMIC
Pre-Silicon:
130nm
EEPROM
,
130nm
G
,
130nm
LL
,
130nm
LV