The interrupt controller monitors interrupts from all other modules within the system and issues interrupt requests to the processor when necessary. The interrupt controller is scalable to support from 1 to 32 interrupt sources. It also provides enable set and enable clear mechanisms to prevent dangerous read-modify-write operations. It provides active high & active low IRQ & FIQ interrupt request outputs.
APB Interrupt Controller
Overview
Key Features
- Programmable Interrupt Controller
- Scalable (from 1 to 32 interrupts)
- Optional programmable interrupt
- AMBA APB interface
- Easily cascaded to support more interrupts
- Separate interrupt enable set and clear mechanisms
- FIQ and IRQ outputs
- Single bit enable and clear control
Block Diagram
Deliverables
- Verilog Source
- Complete Test Environment
- APB Bus Functional Model
- C-Sample Code
Technical Specifications
Maturity
Silicon Proven
Availability
Now
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