The ODT-AFE-12A1P2T-16FFCT is an ultra high-performance AFE designed in a 16nm CMOS process.
The AFE includes eight 12-bit, 2GSPS ADCs, four 12-bit 200MSPS ADCs, two TV monitors, multiple LDOs for ADC supplies, and a low jitter fractional-N PLL.
The ADC architecture is optimized to maximize performance while minimizing power and area consumption.
To maximize SNR, the AFE includes an ultra-low-jitter clock distribution network.
Analog Front End: 8x 12-bit 2 GSPSADCs, 4x 12-bit 200 MSPS ADCs, TVM, PLL, LDO
Overview
Key Features
- Ultra high-performance AFE
- Eight 2GSPS ADCs
- ODT-ADS-12B2G-T16
- Four 200MSPS ADCs
- ODT-ADS-12B200M-T16
- Low jitter PLL
- Two Temperature-voltage monitors
- ODT-TVM-1P0-T16
- Multiple ADC LDOs
- ODT-LDO-IC-250M-16FFCT
- PLL bypass mode
- ADC Clock distribution network
- ADC Clock divider synchronization logic
- Integrated ESD and bumps
Benefits
- High Performance Low Power, Low Area
Applications
- General purpose software defined radio
- High speed data acquisition systems
- Cellular base station
- Broadband communications
- High-speed medical imaging
- Wideband satellite receiver
Deliverables
- Datasheet
- Hard Macro (GDSII)
- Characterization Report (as applicable)
- Abstract View (LEF) for top level connectivity
- Integration and Customer Support
Technical Specifications
Foundry, Node
TSMC 16nm
Maturity
Silicon Characterized
Availability
Now
TSMC
Pre-Silicon:
16nm
Related IPs
- Analog Front End: 16x 12-bit 200 MSPS ADCs, 14x Voltage DACs, 4x 250 MSPS DACs, 4x TVM, LDO
- Analog Front End: 4 channels of 12-bit 2 GSPS ADC IQ Pairs, 4 channels of 12-bit 2 GSPS DAC IQ Pairs, PVT & Integrated PLL
- Analog Front End: 1 channel of 12-bit 2 GSPS ADC IQ Pairs, 1 channel of 12-bit 2 GSPS DAC IQ Pairs, PVT & Integrated PLL
- Analog Front End: 8x 9-bit, 1 GSPS ADCs, PLL
- Single Wire Protocol (SWP) Master Analog Front End (AFE) compliant with the ETSI 102.613 standard
- Single Wire Protocol (SWP) Slave Analog Front End (AFE) compliant with the ETSI 102.613 standard