IP Catalog > Peripheral IP > AMBA AHB / APB/ AXI IP > AMBA AHB / APB IP > AMBA AHB Assertion IP

AMBA AHB Assertion IP

Overview

AMBA AHB Assertion IP provides an efficient and smart way to verify the AMBA AHB designs quickly without a testbench. The SmartDV's AMBA AHB Assertion IP is fully compliant with standard AMBA 2 AHB, AMBA 3 AHB-Lite and AMBA 5 AHB Specifications and provides the following features.

AMBA AHB Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

AMBA AHB Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Specification Compliance
    • Compliant with ARM AMBA 2 AHB, AMBA 3 AHB-Lite and AMBA 5 AHB specifications
    • Supports all ARM AMBA AHB data widths and address widths.
    • Support for all the transfer sizes.
    • Supports all protocol transfer types, burst transfers and response types.
    • Supports locked transfers.
    • Supports Exclusive Transfers.
    • Supports split and retry transfers.
    • Supports unaligned address accesses.
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Master mode, Slave mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV AHB VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure AHB Assertion IP functionality.

    Benefits

    • Runs in every major formal and simulation environment.

    Block Diagram

    AMBA AHB Assertion IP Block Diagram

    Deliverables

    • Detailed documentation of Assertion IP usage.
    • Documentation also contains User's Guide and Release notes.

    Technical Specifications

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