AES256/AES128 IP

Overview

AES-256SS IP specializes in ultra-high throughput and ultra-low latency. IP computes 128-bit data blocks in every 1 clock cycle. Delivering 128Mbps throughput per 1MHz such as 51.2 Gbps @ 400MHz.

AES-128 IP is 1st member of Advanced Encryption Standard (FIPS-197) IP Series, designed to support ECB mode for both encryption and decryption. AES128-IP computes 128-bit data blocks within constant 11 clock cycles. Delivering 11.6Mbps throughput per 1MHz such as 5.8 Gbps @ 500MHz.

AES Encryption IP Series is designed to enhance security features of existing Data Storage and Networking IP Cores. Enabling more opportunity for inventing the secure, efficient and high performance applications.

Key Features

  • Support AES ECB mode standard.
  • Key size
    • AES-128 IP: 128 bit
    • AES-256 IP: 256 bit
  • Support input data width128-bit.
  • High-Throughput rate
    • AES-256SS IP: 51.2 Gbps @400MHz, 128 Mbits/MHz
    • AES-128 IP: 5.8 Gbps @500MHz, 11.6 Mbits/MHz
    • AES-256 IP: 4.26 Gbps @500MHz, 8.53 Mbits/MHz
  • Low Latency
    • AES-256SS IP: 15 clock cycles for 128-bit data calculation
    • AES-128 IP: 11 clock cycles for 128-bit data calculation
    • AES-256 IP: 15 clock cycles for 128-bit data calculation

Block Diagram

AES256/AES128 IP Block Diagram

Technical Specifications

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Semiconductor IP