A/D Converter IP, 12 bits, 80Msps, I-Q Channels, UMC 55nm SP process
Overview
12-Bit 80MSPS Dual-channel Pipelined Analog-to-Digital converter, UMC 55nm SP/RVT Low-K Logic process.
Technical Specifications
Foundry, Node
UMC 55nm SP
UMC
Pre-Silicon:
55nm
Related IPs
- D/A Converter IP, 12 bits, 80Msps, I-Q channels, UMC 55nm SP process
- 12-bit 50/100MSPS SAR A/D Converter in 55nm LL
- ULP 12 Bits, 35 kS/s SAR Analog to Digital Converter
- 12 Bits, 100 kS/s SAR Analog to Digital Converter
- 128x8 Bits OTP (One-Time Programmable) IP, TSMC 55nm LP 1.2V/2.5V & ULP 0.9V/2.5V Mixed-Signal, General Purpose Process
- 4Kx16 Bits OTP (One-Time Programmable) IP, UMC 110 nm 1.2V/3.3V L110AE Process