a 12-bit 1MSPS SAR-ADC on UMC 40nm LP, with 10-channel GPIO integrated
Overview
a 12-bit 1MSPS SAR-ADC on UMC 40nm LP, with 10-channel GPIO integrated
Technical Specifications
Foundry, Node
UMC 40nm Logic/Mixed_Mode LP
UMC
Pre-Silicon:
40nm
,
40nm
LP
Related IPs
- a 10-bit 1-MSPS 11-to-1 SAR-ADC with 11-channel GPIO integrated based on UMC 55nm eFlash process
- 12Bit 1Msps SAR-ADC based on UMC 55nm uLP eflash process (GPIO Function integrated)
- Ultra-low power and high performance 12bit 1Msps SARADC
- 28nm Wirebond IO library with dynamically switchable 1.8V/ 3.3V GPIO, 5V I2C open-drain, 1.8V & 3.3V analog, OTP program cell, and HDMI & LVDS protection macros - featured across a variety of metal stack and pad configuration options
- ISO/IEC 7816-3 digital controller for integrated circuit card compliant with ETSI TS 102 221 and EMV 2000 standards
- 2D (vector graphics) & 3D GPU IP A GPU IP combining 3D and 2D rendering features with high performance, low power consumption, and minimum CPU load