80251 IP

Overview

The DQ80251 is a revolutionary Quad-Pipelined ultra high performance, speed optimized soft core of a 16-bit/32-bit embedded microcontroller. The core is fully configurable and allows selection of its features and peripherals, to create a dedicated system. It has been designed with a special concern of performance to power consumption ratio. This ratio is extended by an advanced power management PMU unit. This product is built based on 14 years of know-how, with triumphant 8051 architectures. The DQ80251 soft core is 100% binary-compatible with industry standard 16-bit 80C251 and 8-bit 80C51 microcontrollers. There are two working modes of the DQ80251: BINARY (where the original 80C51 compiled code is executed) and SOURCE (a native 80C251 mode, using all DQ80251 performance). The DQ80251 has a built-in, configurable DoCD-JTAG on chip debugger, supporting Keil DK251 and standalone DoCD debug software. Dhrystone 2.1 benchmark program runs 66 times faster than the original 80C51 and 5.5 times faster, than the original 80C251 at the same frequency. This performance can be also exploited to great advantage in low power applications, where the core can be clocked over fifty times slower than the original implementation, with no performance penalty. Additionally, the compiled code size for the SOURCE mode is about 2 times smaller comparing to the identical standard 8051 code, due to higher efficiency of DQ80251 instructions. The DQ80251 is delivered with fully automated testbench and complete set of tests, allowing easy package validation at each stage of SoC design flow.
Each of our 80251 cores has a built-in support for Hardware Debug System, called DoCDTM. It is a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC).
Unlike other on-chip debuggers, the DoCDTM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of the microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals.

Key Features

100% binary compatible with industry standard 80C251, implementing BINARY and SOURCE modes
Single clock period per most of instructions
Quad-Pipelined architecture enables to run 66 times faster than the original 80C51 and 5.5 times faster, than the 80C251 at the same frequency
Up to 61.8 VAX MIPS at 100 MHz
Up to 8M bytes of Program Memory
Up to 32k bytes of internal (on-chip) Data Memory
Up to 8M bytes of external (off-chip) Data Memory
Up to 16 MB of total memory space for CODE and DATA
32k bytes of extended stack space
User programmable Program Memory Wait States solution - for wide range of memories' speed
User programmable Extended Data Memory Wait States solution - for wide range of memories' speed
De-multiplexed Address/Data bus, to allow easy connection to memory
Full Program Memory writes
Interface for additional Special Function Registers
Fully synthesizable
Static synchronous design
No internal tri-states
Scan test ready

Block Diagram

Deliverables

Source code:
VHDL Source Code or/and
VERILOG Source Code or/and
Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment
Active-HDL automatic simulation macros
ModelSim automatic simulation macros
Tests with reference responses
Technical documentation
Installation notes
HDL core specification
Datasheet
Synthesis scripts
Example application
Technical support

Technical Specifications

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