The IP consists of a 7 bit monolithic folding ADC clocked externally for 6 GS/s.
The differential input signal of maximum +/- 450 mV is ac-coupled to the input. Lower cut off frequency is well below 500 kHz.
The ADC is calibrated internally after reset to increase precision. The calibration can be disabled and can also be triggered manually.
The reference voltage is either derived from the 1.2 V supply or can alternatively be provided externally.
The IP needs an external clock with high accuracy and low jitter, because the clock jitter may influence the dynamic features of the converter. This clock is used as the sampling clock.
The digital output word of 7 bits is provided as a 4x parallel bus together with the clock.
The ADC is silicon evaluated in Fujitsu 55 nm CS250L technology.
Fraunhofer IIS provides a detailed documentation and support for the IP integration. Modifications, extensions and technology ports of the IP are available on request.
