50-800 MHz phase-locked loop frequency synthesizer
Overview
055TSMC_PLL_01 is an integer-N phase-locked loop frequency synthesizer (PLL), which produces stable clock signal in range from 50 to 800 MHz. It works with reference frequency from 4 to 20 MHz. The block includes 400-800 MHz VCO, programmable N and R dividers, low noise digital phase-frequency detector (PFD), charge pump (CP) with integrated loop filter, frequency lock detector (FLD) and programmable output clock C divider.
Key Features
- TSMC CMOS 55 nm
- Output frequency range from 50 MHz to 800 MHz
- Fully integrated VCO
- Reference frequency range from 4 MHz to 20 MHz
- Low current consumption
Applications
- Frequency clock generation
Deliverables
- Schematic or NetList
- Abstract view (.lef and .lib files)
- Layout (optional)
- Behavioral model (for functional verification)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Technical Specifications
Foundry, Node
TSMC CMOS 55 nm
Maturity
Silicon proven
Availability
Now
TSMC
Silicon Proven:
55nm
FL