40nm 9-bit ultra-low powerADC
Overview
This ADC has 9bit resolution and can support sample rates from DC to 12.5MS/s, this design can be used for a variety of applications such as sensor interfacing and receiver frontends (e.g., BLE, Zigbee, 802.11.ah).
Key Features
- Asynchronous dynamic logic
- INL/DNL <0.5LSB at 1V
- Power consumption scales dynamiclly with the sampling rate
- FoM can be as low as 6.7J/conv.step at 1V
- No calibration
Applications
- Communications
- Data processing
- Consumer Electronics
- Automotive
- Industrial and medical
Deliverables
- Whitebox IP license (including CDS, schematic, layout, extracted, testbenches, scripts, matlab model, a.o. ) with technology transfer training and support
Technical Specifications
Short description
40nm 9-bit ultra-low powerADC
Vendor
Vendor Name
Foundry, Node
TSMC, 40nm
Maturity
Silicon proven on prototypes
Availability
ASIC
TSMC
Silicon Proven:
40nm
G
,
40nm
LP
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