16-Bit, 16kSPS SD ADC

Overview

The L55CSD16B16K IP consists of a 16-bit mono audio ADC with fully differential 1-channel mono audio input, 4-channel general purpose (GP) inputs and a digital microphone input. It also has an analog front end consisting of a microphone bias generator and a wide-range PGA, which offers gains of up to 50dB, allows smaller signals to be measured with high resolution. Analog-to-digital (ADC) employ sigma-delta (SD) modulation with selectable oversampling. ADC includes a digital decimation filter. L55CSD16B16K supports left-justified, I2S compatible and TDM modes. Sampling rates up to 16 kHz are supported.

Figure 1 shows a functional diagram of the L55CSD16B16K. The SD ADC block consists of multiplexers, reference circuits, a fourth-order SD modulator with fully differential architecture and digital decimation filter. The input range of the ADC is limited to between the top-level reference voltage and the bottom-level reference voltage at GP.

Considering the sampling rate of 16kS/s with 1kHz input and full scale input range, the L55CSD16B16K features dynamic performance of the 90dB SNR at Analog Mic path (AMIC).

Key Features

  • 55nm 2P7M SMIC CMOS technology
  • Programmable Gain : 0 to 50dB
  • Selectable Microphone bias : -1.3V/2.5V 2.9V
  • Mono Audio input
  • 4-channel GP fully-differential inputs
  • 16-bit resolution
  • 16kS/s conversion rate
  • Digital serial interface : PDM / I2S / TDM
  • Analog input range : AVSS to AVDD @GP
  • Current consumption : 2.0mA @typ, analog
  • Current consumption : 0.2mA @typ, digital
  • SNR : 90dB @AMIC
  • Power-down current : < 1uA
  • Analog Supply : 1.8V to 3.6V
  • Digital Supply : 1.2V
  • Core Size : 0.4275mm2 @Analog
  • Core Size : 0.0625mm2 @Digital

Applications

  • Audio

Deliverables

  • GDSI, GDSII
  • Verilog-model
  • Datasheet
  • Test plan

Technical Specifications

Foundry, Node
55nm, SMIC
Maturity
Mass Prouction
Availability
Available on request
SMIC
In Production: 55nm G
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Semiconductor IP