125M 9bit 2.5bit pipeline share-OP ADC for 10/100/1000 Ethernet DPHY use; UMC 28nm HPC/Low-K process_x005F_x000D_
Overview
125M 9bit 2.5bit pipeline share-OP ADC for 10/100/1000 Ethernet DPHY use; UMC 28nm HPC/Low-K process
Technical Specifications
Foundry, Node
UMC 28nm Logic/Mixed_Mode HPC
UMC
Pre-Silicon:
28nm
HLP
,
28nm
HPC
,
28nm
HPM
,
28nm
LP
Related IPs
- 0.9V/1.8V 9Bits 125MSPS Pipelined ADC; UMC 28nm HPC+, LowK, Logic Process
- 12b-32MSps Pipeline ADC
- CMM lane operating from 1.25G~8G ,UMC 28nm HPC Process
- Analog part of TX+RX lane operating at 1.25G~8Gbps , UMC 28nm HPC Process
- 14-bit, 4.32Gsps Ultra high speed Wideband, Time-Interleaved Pipeline ADC IP
- 12bit 200Msps High Speed Pipeline ADC IP Core