12-bit 1-channel 4 MSPS SAR ADC
Overview
065TSMC_ADC_10 employs high-performance differential successive approximation architecture with sub-ranging and output offset compensation techniques. The ADC operates with sampling rate up to 4 MSPS and a corresponding input clock up to 52 MHz. The ADC supports standby mode and features low power consumption, compact area.
Key Features
- TSMC CMOS 65 nm
- Resolution 12 bit
- Single power supplies for digital and analog parts (2.5 V)
- Sampling rate up to 4 MSPS
- Clock frequency up to 52 MHz
- Standby mode (current consumption <50 nA)
- Low-power dissipation:
- - 2.5 mW at 4 MSPS
- Spurious-free dynamic range:
- - 71.1 dB at 4 MSPS and Fin = 10.7 MHz
- Signal-to-noise ratio:
- - 53.5 dB at 4 MSPS and Fin = 10.7 MHz
- Compact die area 0.124 mm2
Applications
- WiFi, WiMax
- Mobile communications
- High quality imaging video systems
- Data acquisition systems
- Portable ultrasound and digital beam-forming systems
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Technical Specifications
Foundry, Node
TSMC CMOS 65 nm
Maturity
Silicon under test
Availability
Now
TSMC
Silicon Proven:
65nm
G