112G LR-Max Ethernet PHY for TSMC N5

Overview

Synopsys Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high performance computing applications. The area-efficient PHY provides a low active and standby power solution that supports multiple electrical standards, including PCI Express® (PCIe®) 6.0, 1G to 112Gbps electrical PHY for 400G/800G Ethernet, Cache Coherent Interconnect for Accelerators (CCIX), Compute Express Link (CXL), JESD204C, CPRI, SATA, and other
industry-standard interconnect protocols. Using leading-edge design, analysis, simulation, and measurement techniques, the multi-protocol 112G PHY delivers signal integrity and jitter performance that exceeds the standards electrical specifications.

The configurable transmitter and receiver equalizers along with Continuous Calibration and Adaptation (CCA) enable designers to control and optimize signal integrity and performance across voltage and temperature variations. The multi-protocol 112G PHY provides advanced power management features for both standby and active power. The BERT and internal eye monitorprovide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the DesignWare Physical Coding Sublayer (PCS) and Media Access Control (MAC) for 200G/400G/800G links to deliver a complete solution, reduce design time and help designers achieve first-pass silicon success.

Key Features

Includes one, two, four, eight or sixteen full-duplex transceivers (transmit and receive functions)
North/South & East/West multi-stacking placement with extensive in-house package route escape studies and HFSS simulation
Integrated solution with DesignWare 200G/400G/800G MAC+PCS or DesignWare PCIe 6 controller
Supports back channel initialization, aggregation, bifurcation, and power management
Supports both internal and external reference clock connections to the PHY
Configurable transmitter and receiver equalization, supporting chip-to-chip, port side, backplane interfaces
Optimal receiver jitter tolerance supports a wider range of board layout designs, immunity to interference (cross talk), and reduces design constraints on board signal paths
Fully controllable via the integrated logic core and the test access port (TAP)
Embedded BERT and internal eye monitor

Benefits

Supports 1.25 to 112 Gbps data-rate
Supports PCI Express 6.0, 1G to 400G/800G Ethernet, CCIX, CXL, JESD204C, CPRI, SATA, and OIF CEI LR/MR/VSR Electrical Interfaces protocols
Supports x1 to x16 macro configurations with aggregation and bifurcation
Spread Spectrum Clock (SSC) support for PCIe
PCIe Separate Refclk Independent SSC (SRIS) and power management features
Ethernet Electrical Energy Efficient (EEE)
Reference clock sharing for aggregated macro configurations
ADC/DSP based PVT invariant architecture
Embedded bit error rate tester (BERT) and internal eye monitor
Supports IEEE 1149.6 AC Boundary Scan

Video

Synopsys 112G Ethernet PHY IP on TSMC N5 Performance Results

This TSMC Symposium 2022 demo shows the Synopsys 112G Ethernet PHY IP for long reach successfully interoperating with Amphenol's 2m DAC cable system and showing BER that's seven orders of magnitude better than the specification.

Applications

High performance computing, data center, networking, smart NICs, accelerators
Network switches and routers
Desktops, workstations, servers
5G RRU/BBU
Embedded systems and set-top boxes

Deliverables

Verilog models and test bench, Protocol-specific test bench, Liberty timing views (.lib), LEF abstracts (.lef), CDL netlist (.cdl), Firmware for AN/LT support and SoC software development and debug, GDSII, IP-XACT XML files with register details, ATPG models, IBIS-AMI models, Documentation

Technical Specifications

Foundry, Node

TSMC 5FF

Availability

Contact the Vendor

TSMC

Pre-Silicon: 5nm

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