10M/100M/1G/2.5G Compact Ethernet TSN Switch

Overview

Smallest size 1G Ethernet switch IP in the industry targeted for Automotive, Avionics, and Industrial applications

The 10M/100M/1G/2.5G compact Ethernet TSN Switch IP core is an advanced managed switch targeting automotive, avionics, and industrial applications. It is providing cut-through and supporting the TSN family of standards. It is compliant to several TSN profiles as defined by IEEE while offering the ultimately lowest gate count on the market.

The non-blocking 10M/100M/1G/2.5G compact managed Ethernet TSN switch IP from Comcores enables fine-grained traffic differentiation for rich implementations of packet prioritization enabling per port and per queue shaping on egress ports. The switch supports MAC learning, VLAN 802.1Q, multicast and broadcast as well as support for timing synchronization according to 802.1AS. Each port provides a native interface for GMII Ethernet PHY devices.

Key Features

Delivers Performance

  • Cut-through architecture
  • NETCONF YANG model support
  • MACsec is available for L2 protection
  • Automatic MAC address learning and aging
  • Extensive statistic reporting
  • QoS features like classification, queuing and priorities included optional support for TSN profiles like:
    • IEEE/IEC 60802: Industrial Automation
    • IEEE P802.1DP: Aerospace onboard Ethernet Communications
    • IEEE P802.1DG: Automotive In-Vehicle Communications
    • IEEE P802.1CM: Fronthaul
    • IEEE P802.1DF: Service Provider Networks
    • IEEE 802.1BA: Audio-Video Bridging (AVB) Systems

Highly Configurable

  • Buffer size fully configurable
  • Configurable scheduling
  • Configurable tagging

Easy to Use

  • Solid Verification Environment
  • Fully FPGA evaluation platform capable
  • SW package with driver, gPTP and NETCONF available
  • Supports GMII, RGMII and SGMII for attaching external PHY

Silicon Agnostic

  • Designed in Verilog and targeting both ASICs and FPGAs

Block Diagram

10M/100M/1G/2.5G Compact Ethernet TSN Switch Block Diagram

Deliverables

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:

  • Solid documentation, including User Manual and Release Note
  • Simulation Environment, including Simple Testbed, Test case and Test Script
  • Programming Register Specification
  • Timing Constraints in Synopsys SDC format
  • Access to support system and direct support from Comcores Engineers
  • Synopsys SGDC Files (optional)
  • Synopsys Lint, CDC and Waivers (optional)

Technical Specifications

Short description
10M/100M/1G/2.5G Compact Ethernet TSN Switch
Vendor
Vendor Name
Maturity
Mature
Availability
Available
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Semiconductor IP