The fully integrated Physical Coding Sublayer (PCS), KR4 FEC and Media Access Controller (MAC) core for 25Gbps Ethernet applications are compliant with IEEE 802.3by standard. The interface to the PMA supports a single 10G/25Gbps bi-directional, serial interface. The PCS sublayer includes 66B encoding, transcoding, and scrambling. This Core also supports CPRI-8, 9 and 10 PCS mode configurable through software register.
The north-bound interface from the MAC provides a configurable 64-bit system interface.
The southbound interface performs the mapping of transmitting and receiving data streams (at the PMA layer) to the on-chip SERDES.
10G/25GBASE-R MAC Core
Overview
Key Features
- Integrated MAC and PCS for area efficiency
- Fully compatible with IEEE802.3 2015 and IEEE 802.3by-2016 Standards
- Super low latency with minimized fixed and variable delay for network efficiency.
- Supports 1588v2 time stamps and full error handling
- Supports 802.3br interpersing express traffic and 802.1Qbb priority flow control (PFC)
Benefits
- Proven IP reduces development time and risk
- Upgrade process as the standard evolves
- Supports both 10G/25GBASE-R PMD interfaces
- Support next-generation 25G NRZ SerDes
- Support for a single-lane SERDES interface Optional KR4 FEC (528,514) RS FEC integration
- Optional CPRI-8, 9 & 10 PCS Mode support
- Off-the-shelf, proven technology implementation in FPGAs and ASIC SOC
- Tested and interoperability-proven against Spirent and Viavi test equipment
Block Diagram
