Low Latency Ethernet 10G/25G MAC

Overview

The German Fraunhofer Heinrich-Hertz-Institute (HHI) partners with MLE to commmercialize and market HHI’s proven network technology solutions.  The Low Latency Media Access Controller (MAC) IP Core for 10G/25G Ethernet enables high-bandwidth, low latency Ethernet communication solutions for FPGA-based systems at 10 Gbps or 25 Gbps line rate. 

MLE is a licensee of Fraunhofer HHI, and offers a range of technology services, sublicenses and business models compatible with customer’s ASIC or FPGA project settings, world-wide.

Key Features

  • Platform and device vendor independent core
  • Supports 10G or 25G Ethernet
  • Low Latency, 19.2ns at 64-Bit at 156.25MHz
  • AXI4-Stream protocol support on client transmit and receive interface
  • Low resource usage
  • Deficit Idle Count mechanism to ensure full data rate
  • Padding of short frames (<64 byte)
  • Support for VLAN tagged frames
  • Promiscuous mode support
  • Generation and checking of CRC-32 at full line rate
  • Optional user defined maximum frame length up to 64 kb or complete disabling of frame length check
  • Customization through configuration vector to trade resources for functionality

Block Diagram

Low Latency Ethernet 10G/25G MAC Block Diagram

Technical Specifications

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Semiconductor IP