100 to 1200MHz phase-locked loop
Overview
055TSMC_PLL_08 is a frequency synthesizer with a fractional division ratio and a quadrature output of the heterodyne signal intended for formation, stabilization and frequency modulation (in transmission mode) of the heterodyne signal in the two frequency ranges: 100-150MHz, 200-300MHz, 400-600MHz and 800-1200MHz, as well as for the formation of clock frequency signals from 1.74 to 52MHz. The block is designed to use a 52MHz signal from XTAL or TCXO as a reference frequency.
Key Features
- TSMC CMOS 55 nm
- Output frequency range from 100 MHz to 1200 MHz
- Fully integrated VCO
- Reference frequency 52 MHz
- Minimum step of tuning the local oscillator frequency 3Hz
Applications
- Frequency clock generation
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Technical Specifications
Foundry, Node
TSMC CMOS 55 nm
Maturity
silicon proven
Availability
Now
TSMC
Silicon Proven:
55nm
FL