100 Gbit/s Polar Encoder and Decoder with soft-decision LLR input
Overview
The IPrium-100-Gbps-Polar-Encoder-Decoder IP Core implements Successive Cancellation Polar forward error correction algorithm with fully-parallel and unrolled architecture.
Key Features
- Fully synchronous design, using single clock
- Fully synthesizable drop-in module for FPGAs
- Optimized for high performance and low resources
- Low implementation loss
- Fully verified and real-time tested on a FPGA based development platform
- Considerations for easy ASIC integration
- Validated on IPrium Evaluation Boards
Applications
- 5G communication systems
- Optical links
- Wireless modems
- Systems with the need of high-throughput FEC Codes
Deliverables
- VQM/NGC/EDIF netlists for Intel (Altera) Quartus Prime, Xilinx Vivado/ISE, Lattice Diamond or Microsemi (Actel) Libero SoC
- IP Core testbench scripts
- Design examples for Intel (Altera), Xilinx, Lattice, and Microsemi (Actel) evaluation boards
- Free 1 year warranty and support period
Technical Specifications
Maturity
Silicon proven
Availability
Now, one-off payment, no fees or royalties
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