DLL-based frequency multiplier is a simple to configure and operate block, combining, small area and low current consumption. Block wakes up in “pass-through” mode with redirecting input reference frequency to the output. After being configured and enabled the block waits until DLL locks and then switches output clock signal CLK_OUT to higher frequency. Disabling block switches it back to “pass-through” mode. Any mode switching is glitch-protected.
10 to 200 MHz DLL-based frequency multiplier
Overview
Key Features
- Global Foundries CMOS 55 nm
- 10 – 200 MHz output frequency
- 0.01 – 100 MHz reference frequency
- Glitch-free mode switching
- DLL lock indication
- Flexible configuration
- Multiplication factor 1, 2, 3 or 4
Block Diagram
Applications
- Digital circuit clocking
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Technical Specifications
Foundry, Node
Global Foundries CMOS 55 nm
Maturity
silicon proven
Availability
Now
GLOBALFOUNDRIES
Silicon Proven:
55nm