10-bit 1-channel 1 to 100 MSPS current DAC
Overview
The 10-bit dual high-speed DAC is based on current steering architecture, which provides high-speed conversion rate and good dynamic performance. DAC consists of four principal blocks: adjustable bias, control logic, current source array and current output switches. Device has a feature of adjusting output current, output cascade transistors bias voltage, and entering sleep mode, turning device off. DAC requires 1 V digital supply, 1.8 V digital and analog supply, and digital and analog ground to work properly. Pins dac_adj[4:0] adjust DAC output current and pins vbias_cm0_adj[2:0] adjust output cascades transistors bias voltage.
Key Features
- TSMC CMOS 90 nm
- Dual DAC
- Resolution 10 bit
- 100 MSPS update rate
- High spurious free dynamic range performance up to 25 MHz output
- Differential current output
- Adjustable output current (from 1.8 mA to 20 mA)
- Power dissipation from 5.4 mW to 38 mW (depending on level of output current)
- Reset Mode
- Sleep mode (current consumption less than 200 nA)
- Portable to other technologies (upon request)
Applications
- Wireless infrastructures
- Broadband communications
- Picocell, femtocell base stations
- Medical instrumentation
- Ultrasound transducer excitation
- Signals and arbitrary waveform generators
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Technical Specifications
Foundry, Node
TSMC CMOS 90 nm
Maturity
Silicon proven
Availability
Now
TSMC
Silicon Proven:
90nm
G