090TSMC_ADC_02 is a 10-bit 1-channel successive-approximation register (SAR) analog to digital converter (ADC) circuit with sample rates up to 1 MSPS.
This ADC consist of: input multiplexer block, ADC core, output logic block, clock generator. The ADC core consist of internal DAC, bias, sample and hold circuit, analog voltage comparator. The ADC requires 3.0...3.6 V analog supply and 0.9...1.1 V digital supply voltage, there are standby mode which allow to optimize power consumption for system need.
10-bit 1-channel 1 MSPS SAR ADC
Overview
Key Features
- TSMC 90 nm CMOS technology
- Resolution 10 bit
- Using different power supply 1 V for digital and 3.3 V for analog parts of ADC circuitry
- Standby mode (current consumption <230 nA)
- Power dissipation from 0.69 mW to 3.08 mW
- Spurious-free dynamic range 65 dB
- Portable to other technologies (upon request)
Applications
- Digital cellular phones
- Portable recording devices
- Digital audio workstations
- Remote sensors
- Data logging devices
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Technical Specifications
Foundry, Node
TSMC CMOS 90 nm
Maturity
pre-silicon verification
Availability
Now
TSMC
Silicon Proven:
90nm
G