10/100 Ethernet PHY IP, UMC 0.18um MS process
Overview
10/100 Base-TX Fast Ethernet PHY, UMC 0.18um MMC process.
Technical Specifications
Foundry, Node
UMC 180nm MS
UMC
Pre-Silicon:
180nm
Related IPs
- High performance 8-bit micro-controller with 256 bytes on-chip Data RAM, three 16-bit timer/counters, and two 16-bit dptr; 0.25um UMC Logic process.
- LPDDR3-PHY Command/address block for LightCo ; UMC 40nm LP/RVT Logic Process
- 40nm LPDDR3-PHY Data block for LightCo ; UMC 40nm LP/LVT Logic Process
- CMM lane operating from 1.25G~8G ,UMC 28nm HPC Process
- Analog part of TX+RX lane operating at 1.25G~8Gbps , UMC 28nm HPC Process
- Multi-channel, multi-speed Ethernet universal media access control (MAC) and physical coding sublayer IP (UMAC)