1.8V GPIO, 1.8V to 3.3V Analog in TSMC 180nm BCD

A Flip-Chip compatible I/O Library in TSMC 180nm BCD with 1.8V GPIO, 1.8V to 3.3V Analog, with ultra low-cap/low-leakage 36V+ ESD solutions.

This silicon proven flip-chip compatible library in TSMC 180nm BCD features a 1.8V GPIO, 1.8 to 3.3V analog I/O, and ultralow capacitance and low leakage 36V+ ESD solutions. The I/O librarydoes not have poly orientation issues, and any I/O can be used in any orientation. Currently a standard bondpad does not exist for this library, but it is designed to accommodate any bondpad with a 60um pitch and a less than 75um height. The GPIO can operate at a standard input of 250MHz and an output of 50MHz. The library analog cell can support 5V analog I/Os as well as 1.8V. The high voltage cells in the libraries can support 36V+, providing low capacitance and low leakage. The library also supports I2C, DDC, CEC and SMBus standards. The library includes all layout and support cells. ESD targets are 2kV HBM and 500V CDM, although the I/Os have passed >4kV HBM and >800V CDM in silicon, depending on packaging. Latch-up immunity has passed >150mA.

Operating Conditions

Cell Summary

ESD Summary

• ESD targets of 2kV HBM and 500V CDM, has passed >4kV HBM and >800V CDM

Standards

• I2C
• DDC
• CEC
• SMBus