180TSMC_PFD_02 is a phase-frequency detector (PFD) forms a control signal for VCO tuning. PFD compares phases of a divided VCO signal and a divided reference oscillator signal and detects phase difference. Charge pump (CP) generates pulses for the loop filter. The lock detector monitors the current status of PLL by comparing the phase difference of VCO divided signal and reference oscillator signal with required value. LD_MP<1:0> and LD_ACR outputs set the lock monitoring period and the lock detector accuracy, respectively.
0.32 to 10 MHz Phase-frequency detector
Overview
Key Features
- TSMC BiCMOS SiGe 180 nm
- Input signals with low amplitude
- Low disbalance of output current
- VCO divided signal buffering and optimization
- High accuracy
- Reference frequency from 0.32 MHz to 10 MHz
- Portable to other technologies (upon request)
Block Diagram
Applications
- Phase-locked loop synthesizer
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Technical Specifications
Foundry, Node
TSMC BiCMOS SiGe 180 nm
Maturity
Silicon proven
Availability
Now
TSMC
Silicon Proven:
180nm
Related IPs
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- 24.84 MHz Phase-frequency detector with charge pump
- 24.84 MHz phase-frequency detector with charge pump