180TSMC_PFD_01 is a phase-frequency detector (PFD) forms a control signal for VCO tuning. PFD compares phases of a divided VCO signal and a divided reference oscillator signal and detects phase difference. Charge pump (CP) generates pulses for the loop filter. The structure consists of two types of PFD with CP: ECL and CMOS choosing by a bit PFD_TP. The lock detector monitors the current status of PLL by comparing the phase difference of VCO divided signal and reference oscillator signal with required value. LD_MP<1:0> and LD_ACR outputs set the lock monitoring period and the lock detector accuracy, respectively.
24.84 MHz Phase-frequency detector with charge pump
Overview
Key Features
- TSMC BiCMOS SiGe 180 nm
- Input signals with low amplitude
- Low disbalance of output current
- Reference frequency 24.84 MHz.
- High accuracy
- Portable to other technologies (upon request)
Applications
- Phase-locked loop synthesizer
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Technical Specifications
Foundry, Node
TSMC BiCMOS SiGe 180 nm
Maturity
Silicon proven
Availability
Now
TSMC
Silicon Proven:
180nm
Related IPs
- 24.84 MHz Phase-frequency detector with charge pump (input amplitude 150…210 mV)
- PLL 24.84 MHz phase-frequency detector with charge pump
- 24.84 MHz phase-frequency detector with charge pump
- 0.1 to 25 MHz Phase-frequency detector with charge pump
- 1 to 20 MHz Phase-frequency detector and charge pump
- PLL CMOS phase-frequency detector with ECL charge pump