Webinar: Accelerating Verification Closure with PCIe Gen4 VIP
In a recent post, Paul Graykowski introduced Synopsys VIP for PCIe Gen4.
To dive deeper into the verification closure process, you can now register for our Webinar on August 14th here.
Today’s PCIe verification engineers have to tradeoff between verification completeness and shrinking to market complicated even further with the new Gen4 specification. Synopsys VC VIP for PCIe, fully compliant to latest version of the Gen4 specification, can solve the riddle of completing verification while keeping with the tight schedules.
This webinar will highlight enhancements to the PCIe specifications (Gen 1, 2, 3 and 4) as reported by PCI-SIG, and provide an overview of the complete PCIe Solution offered by Synopsys – Controller, PHY and VIP. It will then dive deeper into Synopsys Verification IP offering, including Test Suites, built-in error injection, passive monitor, and it will also touch on NVMe support. We will conclude with a demo using Verdi Protocol Analyzer to demonstrate advance features for debugging complex verification scenarios.
Register
Web event: Learn How to Accelerate Verification Closure with PCIe Gen4 VIP
Date: August 19, 2015
Time:10:00 AM PDT
Related Semiconductor IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
- High Speed Ethernet 2/4/8-Lane 200G/400G PCS
Related Blogs
- PCIe PIPE 4.4.1: Enabler for PCIe Gen4
- Introducing Synopsys VIP for PCIe Gen4
- PCIe Gen4 - VIP/IP Solution with Protocol-Aware Debug and Source Code Test Suites
- PCIe Gen4 Test Suite with Spec Linking Demo
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?