Solve SoC Bottlenecks with Smart Local Memory in AI/ML Subsystems
In today’s disaggregated electronics supply chain the (1) application software developer, (2) the ML model developer, (3) the device maker, (4) the SoC design team and (5) the NPU IP vendor often work for as many as five different companies. It can be difficult or impossible for the SoC team to know or predict actual AI/ML workloads and full system behaviors as many as two or three years in advance of the actual deployment. But then how can that SoC team make good choices provisioning compute engines and adequate memory resources for the unknown future without defaulting to “Max TOPS / Min Area”?
There has to be a smarter way to eliminate bottlenecks while determining the optimum local memory for AI/ML subsystems.
To read the full article, click here
Related Semiconductor IP
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- ML-KEM Key Encapsulation & ML-DSA Digital Signature Engine
- MIPI SoundWire I3S Peripheral IP
- ML-DSA Digital Signature Engine
- P1619 / 802.1ae (MACSec) GCM/XTS/CBC-AES Core
Related Blogs
- High Speed Memory in Smart Phones: MIPI UniPro v1.8 for JEDEC UFS v3.0
- Boost SoC Flexibility: 4 Design Tips for Memory Subsystems with Combo DDR3/4 Interfaces
- Faster Embedded Smartphone & Tablet Memory Is On The Way
- Building Smarter, Faster: How Arm Compute Subsystems Accelerate the Future of Chip Design
Latest Blogs
- How Network-on-Chip Architectures Are Powering the Future of Microcontroller Design
- PCIe Low-Power Validation Challenges and Potential Solutions (PIPE/L1 Substates)
- Rethinking Edge AI Interconnects: Why Multi-Protocol Is the New Standard
- Tidying Up: FIPS-Compliant Secure Zeroization for OTP
- Accelerating Your Development: Simplify SoC I/O with a Single Multi-Protocol SerDes IP