Solve SoC Bottlenecks with Smart Local Memory in AI/ML Subsystems
In today’s disaggregated electronics supply chain the (1) application software developer, (2) the ML model developer, (3) the device maker, (4) the SoC design team and (5) the NPU IP vendor often work for as many as five different companies. It can be difficult or impossible for the SoC team to know or predict actual AI/ML workloads and full system behaviors as many as two or three years in advance of the actual deployment. But then how can that SoC team make good choices provisioning compute engines and adequate memory resources for the unknown future without defaulting to “Max TOPS / Min Area”?
There has to be a smarter way to eliminate bottlenecks while determining the optimum local memory for AI/ML subsystems.
To read the full article, click here
Related Semiconductor IP
- USB 20Gbps Device Controller
- AGILEX 7 R-Tile Gen5 NVMe Host IP
- 100G PAM4 Serdes PHY - 14nm
- Bluetooth Low Energy Subsystem IP
- Multi-core capable 64-bit RISC-V CPU with vector extensions
Related Blogs
- High Speed Memory in Smart Phones: MIPI UniPro v1.8 for JEDEC UFS v3.0
- Boost SoC Flexibility: 4 Design Tips for Memory Subsystems with Combo DDR3/4 Interfaces
- Faster Embedded Smartphone & Tablet Memory Is On The Way
- Building Smarter, Faster: How Arm Compute Subsystems Accelerate the Future of Chip Design
Latest Blogs
- From guesswork to guidance: Mastering processor co-design with Codasip Exploration Framework
- Enabling AI Innovation at The Far Edge
- Unleashing Leading On-Device AI Performance and Efficiency with New Arm C1 CPU Cluster
- The Perfect Solution for Local AI
- UA Link vs Interlaken: What you need to know about the right protocol for AI and HPC interconnect fabrics