Re-targetable LLVM C/C++ compiler for RISC-V
RISC-V is a modular instruction set architecture (ISA) with great customization capabilities that enable innovation and differentiation without fragmentation. On top of the baseline modules from ratified/standard ISA extensions, such as integer instructions or floating-point instructions, designers can add custom instructions: pure design freedom! And the reasons for adding instructions are many: better performance, smaller memory footprint, lower power consumption, or anything in between.
This means one important thing: the software (the final application(s)) is compiled for the particular RISC-V ISA. The software development kit (SDK) must know which ISA modules the RISC-V processor implements, so it can automatically leverage them. This includes both standard instructions and custom instructions.
But how do you get the best SDK for a given RISC-V ISA? Let’s have a look in this blog as we focus on the C/C++ compiler, an essential part of the SDK. The compiler must, as much as possible, be able to automatically and wisely use instructions.
What is an LLVM C/C++ compiler?
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Related Semiconductor IP
- RISC-V CPU IP
- RISC-V Vector Extension
- RISC-V Real-time Processor
- RISC-V High Performance Processor
- 32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
Related Blogs
- Configurable LLDB for (not only) embedded RISC-V processors
- RISC-V: An Open Standard - Backed by a Global Community - to Enable Open Computing for All
- RISC-V Summit report: Meta leads the way for custom processors
- Navigating Integration Challenges for the RISC-V Ecosystem with Networks-on-Chips (NoCs)
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