Memory VIP Challenges
May 28, 2015
Behavioral Memory Models have been used for verification purposes for several years now. In the early days, modeling technology didn’t add much value to the usage model as designs were simple.
With increasing design complexity, and demand for more functionality driving SoC complexity and cost, memory verification models need to morph into a state that can ensure that memory requirements meet the demand of the design. A realistic way to achieve this is to develop these models in the most commonly used design and verification language, SystemVerilog.
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