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ARC4 Core for Xilinx FPG

Overview

The Helion ARC4 core implements the Alleged RC4 stream cipher algorithm. The RC4 algorithm itself was developed by Ron Rivest in 1987 and was originally a trade secret of RSA Security. However, a description of the algorithm became widely available on the Internet in 1994 and so the algorithm is no longer considered a trade secret, although the name RC4 itself is still trademarked. Legal third party implementations are therefore often referred to as Alleged RC4, which is usually abbreviated to ARC4.

The Helion ARC4 core generates a byte-wide keystream which is used to perform encryption and decryption when XOR’ed with either plaintext or ciphertext. It supports variable length key sizes of up to 16 bytes long. Applications include hardware implementations of the WEP and WPA 802.11i wireless security protocols, as well as TLS/SSL (Transport Layer Security, formerly Secure Sockets Layer) applications.

Key Features

  • Implements ARC4 stream cipher algorithm
  • Fully compliant with the requirements of 802.11i WPATM (WEP/TKIP) and SSL/TLS
  • High speed operation – processes at a rate of 3 clocks per data byte
  • Supports variable length keys up to 16 bytes long
  • Efficient re-keying to minimise effective key setup time
  • Simple external interface
  • Highly optimised for use in Xilinx FPGA technologies

Block Diagram

ARC4 Core for Xilinx FPG Block Diagram

Deliverables

  • Target specific netlist or fully synthesisable RTL VHDL/Verilog
  • VHDL/Verilog simulation model and testbench
  • User documentation

Technical Specifications

Short description
ARC4 Core for Xilinx FPG
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