xSPI PHY IP
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Host controller IP for controlling flash and other devices on the SPI bus: Quad SPI, Octal SPI, and xSPI
- Flexibility: Multiple SPI protocol support within single IP
- Simplicity: PHY-less IoT operation, or soft storage combo PHY IP simplifies SoC timing
- High Performance: Supports maximum Quad SPI / Octal SPI data rates and XIP (Execute In Place)
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xSPI, HyperBus™, and Xccela™ Serial Memory Controller
- The xSPI-MC core is a versatile serial/SPI memory controller, which allows a system to easily detect and access the attached memory device or directly boot from it.
- The controller core supports most of the proprietary SPI protocols used by Flash and PSRAM device vendors and is compatible to JEDEC’s eXpanded SPI (xSPI), HyperBus™ and Xccela™ standards.
