The xSPI-MC core is a versatile serial/SPI memory controller, which allows a system to easily detect and access the attached memory device or directly boot from it. The controller core supports most of the proprietary SPI protocols used by Flash and PSRAM device vendors and is compatible to JEDEC’s eXpanded SPI (xSPI), HyperBus™ and Xccela™ standards.
The core allows the system to interface with one or more serial memory devices in one of the following modes: a) in Slave mode by accessing its registers via an AHB slave interface, b) in DMA mode where the system programs the internal DMA engine, and then the core accordingly drives its AHB master interface, c) in Access In-Place (AIP) mode where the core allows the system to directly access the SPI memory address space via an AHB or AXI slave interface, d) in Boot-Image copy mode where after reset the core will autonomously copy an amount of data (boot-image) from the SPI memory to the AHB address space (e.g. on a shadow RAM, or DRAM) using its AHB master interface.
xSPI-MC can work with single, dual, quad, twin-quad, octal or 16x SPI memory devices. To enable use with memory devices from different vendors, the core offers two ways of configuring the device-specific parameters: a) via registers, where the system is responsible to identify the connected flash device and program the appropriate values to the core's registers, and b) by using the auto-configuration feature, where the core will autonomously identify the connected memory device and program itself accordingly. The auto-configuration functionality uses a user-provided memory that stores a list of automatically identifiable devices along with their features.
The xSPI-MC can be easily configured to match different application requirements. The instantiation of the DMA engine and the auto-configuration logic, the maximum number of memory devices that the core supports, and the reset values for all configuration registers, are some of the design parameters that can be controlled by means of simple Verilog defines.
The core can be implemented in any ASIC or FPGA technology, as it is delivered with a synthesizable soft-PHY, and does not use any process-specific modules. Sample timing constraints are provided with the core and optional technology mapping support is available.
