ultra-low voltage memory IP
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Ultra-low voltage, SRAM
- SureCore has exploited its low power design capability to create a new range of ultra-low voltage, SRAM solutions, called PowerMiser™ Plus.
- Based on the market-leading, low dynamic power PowerMiser architecture, this dual rail product family can interface down to 0.45V, enabling customers to create innovative, low power products.
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Low Power Memory Compiler - 1-Port Register File Compiler - GF 22nm FDX
- Specifically designed for ultra-low power applications, this memory leverages body biasing to dramatically reduce power consumption.
- Compatible with industry Adaptive Body Biasing IP for PVT and aging compensation
- Body Biasing functionality (up to +1.3V / -1.5V) to reduce leakage or increase speed at the same power
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MIPI M-PHY HS-G4 IP (M-PHY v4.1) in TSMC 40G
- Supports MIPI® Alliance Specification for M- PHY® Version 4.1.
- Dual-simplex point-to-point interface with ultra-low voltage differential signaling.
- Slew-rate control for EMI reduction.
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Single Rail SRAM GLOBALFOUNDRIES 22FDX
- Single port SRAM compiler based on Racyics® R188 logic memory cell with dual-well architecture
- Supply voltage 0.55 V to 0.8 V enabled with Racyics® ABB
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Dual-Rail SRAM Globalfoundries 22FDX
- Single port SRAM compiler based on P124 bitcell with Dual-supply-rail architecture
- Bitcell array supply voltage 0.8V and ULV core interface down to 0.4V enabled with Racyics' ABB
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ReRAM NVM in SkyWater 130nm
- Technology: 130nm, SkyWater S130
- Mask Adder: 2
- Supply Voltage: 1.8V Read, 1.8V+3.3/3.6V Program
- Read Access Time: <20nsec
- Operation Temp.: -40°C - 125°C (can be extended to -55°C)
- Capacity: 256 Kbit (can be customized for 128Kbit - 2Mbit)
- Data Bus Width (Read): 32-bit (can be customized to 16-bit to 128-bit)
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TLS 1.3 Compliant Crypto Coprocessor
- NIST CAVP certified and OSCCA standard compliant crypto engine suite
- Includes private/public key ciphers, message authentication code, hashes, and key derivation
- Key wrapping function for the secure export of keys
- Public-key coprocessor for digital signatures and key agreements over elliptic/Edward curves
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Crypto Coprocessor
- Comprehensively support all CPU architectures
- Crypto engine collective, consisting of private key cipher, message authentication code, hash, and key derivation functions that are NIST CAVP certified and OSCCA standards compliant
- Key wrapping function aiding the export of keys for external use
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Ultra low power BLE 5.0 / ZigBee / Thread SoC - custom Modification, White Label chips
- 32bit proprietary MCU: Better power performance then ARM M0 with max speed of 48Mhz
- Memory: Program memory: 512kB Flash, 64kB on-chip SRAM with up to 32kB retention
- RF transceiver: BLE 5.1 Compliant, 1Mbps, 2Mbps, Long Range 125kbps and 500kbps Or 2.4GHz proprietary 1Mbps/2Mbps/250kbps/500kbps mode with Adaptive
- Frequency Hopping feature or 15.4 compliant, 250kbps