ultra low power PLL IP
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31
IP
from 10 vendors
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Ultra low Power High Speed 150MHz integer-N PLL IP Core
- Integer Division
- High Stability
- Designed to be power-efficient
- Low Jitter
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Ultra low Power High Speed 400MHz lnteger-N PLL IP Core
- Integer Division
- High Stability
- Designed to be power-efficient
- Low Jitter
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Ultra low Power High Speed 500MHz integer-N PLL IP Core
- Integer Division
- High Stability
- Designed to be power-efficient
- Low Jitter
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Ultra low Power High Speed 600MHz lnteger-N PLL IP Core
- Integer Division
- High Stability
- Designed to be power-efficient
- Low Jitter
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Ultra low Power High Speed 800MHz Frac-N PLL IP Core
- Designed to be power-efficient
- Fractional Division
- High Resolution of 800MHz
- Low Jitter
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Ultra low Power 1.4GHz Frac-N PLL IP Core
- Designed to be power-efficient
- Fractional Division
- High Resolution of 1.4GHz
- Low Jitter
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Analog Front End: 1 channel of 12-bit 2 GSPS ADC IQ Pairs, 1 channel of 12-bit 2 GSPS DAC IQ Pairs, PVT & Integrated PLL
- Ultra high-performance AFE
- FR1/FR2- I/Q ADCs 12-bit 2GSPS
- FR1/FR2 – I/Q DAC 12-bit 2GSPS
- Capless LDOs
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Analog Front End: 8x 12-bit 2 GSPSADCs, 4x 12-bit 200 MSPS ADCs, TVM, PLL, LDO
- Ultra high-performance AFE
- Eight 2GSPS ADCs
- ODT-ADS-12B2G-T16
- Four 200MSPS ADCs
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Complete 1.6T Ultra Ethernet IP Solution
- Ethernet MAC, PCS and PHY to complete a full Ultra Ethernet interface stack
- Supports evolving IEEE 802.3 and OIF-224G electrical standards
- Provides support for 4 x 400G, 2 x 800G, and 1.6T Ethernet rates using 112Gbps and 224Gbps SerDes
- Meets performance criteria for chip-to-chip, chip-to-module, and long reach copper/backplane interconnects
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MIPI D-PHY Bidir 2/4L
- ? Attachable PLL clock multiplication unit for master-side functionality
- ? Flexible input clock reference — 5 MHz to 500 MHz
- ? 50% DDR output clock duty-cycle
- ? Lane operation ranging from 80 Mbps to 1.5 Gbps in forward direction