ultra low power PLL IP
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125
IP
from 11 vendors
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Ultra low Power High Speed 150MHz integer-N PLL IP Core
- Integer Division
- High Stability
- Designed to be power-efficient
- Low Jitter
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Ultra low Power High Speed 400MHz lnteger-N PLL IP Core
- Integer Division
- High Stability
- Designed to be power-efficient
- Low Jitter
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Ultra low Power High Speed 500MHz integer-N PLL IP Core
- Integer Division
- High Stability
- Designed to be power-efficient
- Low Jitter
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Ultra low Power High Speed 600MHz lnteger-N PLL IP Core
- Integer Division
- High Stability
- Designed to be power-efficient
- Low Jitter
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Ultra low Power High Speed 800MHz Frac-N PLL IP Core
- Designed to be power-efficient
- Fractional Division
- High Resolution of 800MHz
- Low Jitter
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Ultra low Power 1.4GHz Frac-N PLL IP Core
- Designed to be power-efficient
- Fractional Division
- High Resolution of 1.4GHz
- Low Jitter
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95 dB of SNR, 24-bit stereo audio CODEC with AGC and headphone output
- PLL-less solution to avoid jitter issue due to audio PLL on SoC
- Pop-Up Noise Reduction system
- High audio performances measurable with test equipment not specific to audio measurement
- Optimal sound recording performances thanks to the Automatic Gain Control
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SMIC 0.18um 24Bit Sigma-Delta DAC
- Process: SMIC standard 0.18um /3.3V logic 1P6M
- Single-Ended DAC --THDN:-90dB@-6dB Fs Input --Dynamic Range, SNR: 100dB
- Audio Serial Interface --32bit word length --I2S mode
- 2-wire Serial Control Interface
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MIPI D-PHY Bidir 2/4L
- ? Attachable PLL clock multiplication unit for master-side functionality
- ? Flexible input clock reference — 5 MHz to 500 MHz
- ? 50% DDR output clock duty-cycle
- ? Lane operation ranging from 80 Mbps to 1.5 Gbps in forward direction
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Audio CODEC with 100 dB SNR, 24-bit stereo channels and cap-less headphone driver
- Fast and easy integration with embedded analog I/O cells
- Pop-up Noise Reduction System with predictable level
- Embedded voltage regulator ensures the best resilience to noise from power supply and minimizes the bill of material
- Programmable biasing circuit for ultra low power mode
