Ultra low Power High Speed 500MHz integer-N PLL IP Core

Overview

A programmable on-the-fly Fractional-N PLL at 500MHz is required to lock to an incoming clock source and produce an output clock available at 22nm.

Key Features

  • Integer Division
  • High Stability
  • Designed to be power-efficient
  • Low Jitter
  • Programmable Loop Filter
  • Lock Detection
  • Small Footprint designed to be compact

Deliverables

  • GDSII
  • LVS Spice netlist
  • Verilog model
  • LEF for clock generator
  • PLL
  • User Guidelines including: integration guidelines, layout guidelines, testability guidelines, packaging guidelines, board-level guidelines

Technical Specifications

Maturity
In Production
Availability
Immediate
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Semiconductor IP