pll IP
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5 GHz 250 fs Jitter PLL - GlobalFoundries 22nm
- The PLL5G250F is an ultra-low power phase locked loop (PLL) intellectual property (IP) block.
- The PLL5G250F features a very small area footprint, with exceptional jitter performance in its power/area class and flexible programmability, making this IP ideal for a wide range of general purpose clocking and specialized applications.
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General Purpose All Digital Fractional-N PLL in UMC 40LP
- Low jitter (< 18ps RMS)
- Small size (< 0.01 sq mm)
- Low Power (< 3.5mW)
- Support for multi-PLL systems
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Low Power All Digital Fractional-N PLL in TSMC N6/N7
- Low power, suitable for IoT applications
- Good jitter, suitable for clocking digital logic.
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
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Low Power All Digital Fractional-N PLL in Samsung 14LPP
- Low power, suitable for IoT applications
- Good jitter, suitable for clocking digital logic.
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
- Reference clock from 5MHz to 200MHz
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Low Power All Digital Fractional-N PLL in GlobalFoundries 12LPP/14LPP
- Low power, suitable for IoT applications
- Good jitter, suitable for clocking digital logic.
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
- Reference clock from 5MHz to 200MHz
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Low Power All Digital Fractional-N PLL in Samsung 8LPP
- Low power, suitable for IoT applications
- Good jitter, suitable for clocking digital logic.
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
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Integer PLL on Samsung 8nm LN08LPP
- PLLF0816X is a 1.8V/0.75V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis.
- It consists of a phase frequency detector (PFD), a charge pump, a voltage-controlled oscillator (VCO), a 6-bit pre divider, a 10-bit main-divider, a 3-bit scaler, and an automatic frequency control (AFC).
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Integer PLL on Samsung 28nm LN28FDS
- PLL2851X is a 1.8V/1.0V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis.
- It consists of a phase frequency detector (PFD), a charge pump, a voltage-controlled oscillator (VCO), a 6-bit pre divider, a 10-bit main-divider, a 3-bit scaler, a lock detector and an automatic frequency control (AFC). The maximum output frequency of PLL is 2.5GHz.
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Frac-N PLL on Samsung 8nm LN08LPP
- PLLF0842X is a 1.8V/0.75V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis.
- It consists of a phase frequency detector (PFD), a charge pump, a voltage-controlled oscillator (VCO), a 6-bit pre divider, a 10-bit main-divider, a 3-bit scaler, a delta-sigma modulator (DSM) and an automatic frequency control (AFC).
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Frac-N PLL on Samsung 4nm LN04LPP
- PLLF0434X is a 1.2V/0.75V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis.
- It consists of a phase frequency detector (PFD), a charge pump, a voltage-controlled oscillator (VCO), a 6-bit pre-divider, a 10-bit main-divider, a 3-bit scaler, a delta-sigma modulator (DSM) and an automatic frequency control (AFC).
