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Search (186)
Compare 186 IP from 37 vendors (1 - 10)
  • TSMC CLN12FFC Chip Performance Monitor
    • TSMC 12nm 0.8V/1.8V CMOS Logic FinFET Compact Process
    • Metal Scheme: 1P7M (2Xa1Xd_h_3Xe_vhv) or above
    • Support one clone critical path ring oscillator customization
    • Maximum 32 internal ring oscillators
  • TSMC CLN7FF Chip Performance Monitor
    • Supports one clone critical path ring oscillator customization
    • Maximum 32 internal ring oscillators
    • Supply voltage range: -20 % to +50 %, from 0.6 V to 1.125 V
    • (Typ. 0.75 V)
  • TSMC CLN5FF Chip Performance Monitor
    • TSMC 5 nm 0.75 V/1.2 V CMOS LOGIC FinFET Process
    • Metal scheme: 1P16M (1X_h_1Xb_v_1Xe_h_1Ya_v_1Yb_h_4Y_vhvh_2Yy2Yx2R) or above
    • Support one clone critical path ring oscillator customization
    • Maximum 32 internal ring oscillators
  • Single channel ADAS chip with FuSa monitor
    • The SFA 250A has been designed to be easy to adapt to suit the support needs of the customer’s IP as it is scalable, both in terms of function and performance, as well as modular as multiple versions can be combined to form larger solutions.
    Block Diagram -- Single channel ADAS chip with FuSa monitor
  • USB 1.1
    • USB 1.1 Device
    • USB 1.1 Hub
  • UFS Hardware Validation Platform (HVP)
    • Compliant to JEDEC UFS 1.0, HCI 1.0, UniPro 1.40
    • Available in Host and Device configuration
  • RFFE Slave IP Core
    • Compliant with MIPI’s RFFE specification Rev 3.0
    • Small silicon footprint
    • Scalable Implementation
    • Up to 15 Devices can be connected per Bus
    • Low pin count on Interface side (SCLK and SDATA)
    Block Diagram -- RFFE Slave IP Core
  • RFFE Master IP Core
    • Compliant with MIPI RFFE Specification 3.0
    • Delivered in Reuse Methodology Manual (RMM) compliant Verilog RTL format
    • Optionally delivered as a physical design
    • Small footprint
    Block Diagram -- RFFE Master IP Core
  • 2.0 RFFE Master IP
    • The MIPI RFFE bus is is 2-wire serial interface which utilizes a bus frequency of up to 26 MHz and timing accurate trigger mechanisms to allow control of timing critical functions.
    • It is used to connect a digital RFIC to RF front end components, like Power Amplifiers, Low-Noise Amplifiers and Antenna Sensors, which are considered RFFE Slaves

     

    Block Diagram -- 2.0 RFFE Master IP
  • Voltage Monitor with Digital Output (Multi-domain supply monitoring), TSMC N3E
    • Accurately measures core supply domain and IO voltages
    • Measurement of supply ranges up to 1.5V (with Prescaler)
    • Measurement of IR drops between supply pins and critical blocks
    • Digital interface for simplified chip integration
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Semiconductor IP