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"asic.foundry_node_process" => [] "asic.node" => [] "asic.node_foundry" => [] "blockdiagram" => "" "category.id" => array:1 [ 0 => 324 ] "category.name" => array:1 [ 0 => "USB 3.0 Controller IP" ] "category.slug" => [] "created_at" => 1504090788 "id" => "11499" "keyfeatures" => "" "keyfeatures_cn" => "" "keywords" => "" "logo" => "faraday-66bb478704cf6.webp" "logo2" => "faraday-66bb478704cf6.webp" "name" => "asic.node" "overview" => "USB3.0 OTG controller with AXI interface, support Host, Peripheral and OTG function" "overview_cn" => "" "partnumber" => "FOTG330" "priority" => 1 "priority_taxo" => 0 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 246 "provider.name" => "Faraday Technology " "provider.object" => "{"id":246,"name":"Faraday Technology ","providerslug":"faraday-technology"}" "provider.priority" => 301 "provider.slug" => "faraday-technology" "published_as_new_at" => 0 "seofeatures" => "" "seofeatures_cn" => "" "shortdescription" => "USB3.0 OTG controller with AXI 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"asic.foundry_node" => [] "asic.foundry_node_process" => [] "asic.node" => [] "asic.node_foundry" => [] "blockdiagram" => "" "category.id" => array:3 [ 0 => 97 1 => 324 2 => 384 ] "category.name" => array:3 [ 0 => "USB Controller IP" 1 => "USB 3.0 Controller IP" 2 => "USB On-The-Go Controller IP" ] "category.slug" => [] "created_at" => 1385624115 "id" => "5501" "keyfeatures" => "" "keyfeatures_cn" => "" "keywords" => "USB3.0 Superspeed OTG Controller" "logo" => "wwago-66bb4783aec17.webp" "logo2" => "wwago-66bb4783aec17.webp" "name" => "asic.node" "overview" => """ WWAGO USB3.0 SS-OTG controller IP is compliant with OTG&EH3.0. USB3.0 SS-OTG controller is able to dynamically swap host/peripheral roles while operating at SuperSpeed using Role Swapping Protocol (RSP) as defined in OTG&EH3.0 specification. The IP is capable of handling multiple devices when acting as Host. \n \n On-The-Go 3.0 is an upgrade to On-the-Go 2.0 and is backwards compatible with past versions. The Embedded Host supplement adds details on how smart appliances like tablets, phones and even cameras will be able to use a single USB 3.0 port as either a host or peripheral. \n \n With this USB3.0 SuperSpeed OTG core from WWAGO, SOC designers will speed up their SOC design with rich function. """ "overview_cn" => "" "partnumber" => "USB3.0 SS-OTG controller" "priority" => 1 "priority_taxo" => 0 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 229 "provider.name" => "WWAGO Inc." "provider.object" => "{"id":229,"name":"WWAGO Inc.","providerslug":"wwago-inc"}" "provider.priority" => 1 "provider.slug" => "wwago-inc" "published_as_new_at" => 0 "seofeatures" => "" "seofeatures_cn" => "" "shortdescription" => "USB3.0 Superspeed OTG Controller" "shortdescription_cn" => "" "slug" => "usb3-0-superspeed-otg-controller" "sortable_id" => 5501 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:1 [ 0 => 7 ] "taxo2" => array:1 [ 0 => 64 ] "taxo3" => array:3 [ 0 => 380 1 => 381 2 => 383 ] "taxo4" => array:3 [ 0 => 97 1 => 324 2 => 384 ] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "USB3.0 SS-OTG controller Superspeed OTG Controller WWAGO Inc." "text_low_priority" => """ WWAGO USB3.0 SS-OTG controller IP is compliant with OTG&EH3.0. able to dynamically swap host/peripheral roles while operating at SuperSpeed using Role Swapping Protocol (RSP) as defined in OTG&EH3.0 specification. The capable of handling multiple devices when acting Host. \n \n On-The-Go 3.0 an upgrade On-the-Go 2.0 and backwards compatible past versions. Embedded Host supplement adds details on how smart appliances like tablets phones even cameras will be use a single USB port either host or peripheral.\n \n With this OTG core from SOC designers speed up their design rich function. """ "text_medium_priority" => "USB3.0 Superspeed OTG Controller " "updated_at" => 1385693940 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ "matched_tokens" => array:4 [ 0 => "USB3.0" 1 => "controller" 2 => "OTG" 3 => "Controller" ] "snippet" => "USB3.0 SS-OTG controller Superspeed OTG Controller WWAGO Inc." ] "text_low_priority" => array:2 [ "matched_tokens" => array:2 [ 0 => "USB3.0" 1 => "controller" ] "snippet" => "WWAGO USB3.0 SS-OTG controller IP is compliant with" ] ] "highlights" => array:2 [ 0 => array:3 [ "field" => "text_high_priority" "matched_tokens" => array:4 [ 0 => "USB3.0" 1 => "controller" 2 => "OTG" 3 => "Controller" ] "snippet" => "USB3.0 SS-OTG controller Superspeed OTG Controller WWAGO Inc." ] 1 => array:3 [ "field" => "text_low_priority" "matched_tokens" => array:2 [ 0 => "USB3.0" 1 => "controller" ] "snippet" => "WWAGO USB3.0 SS-OTG controller IP is compliant with" ] ] "text_match" => 1763185779749683202 "text_match_info" => array:7 [ "best_field_score" => "3315704266752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1763185779749683202" "tokens_matched" => 3 "typo_prefix_score" => 0 ] ] 2 => array:5 [ "document" => array:48 [ "asic.foundry" => [] "asic.foundry_node" => [] "asic.foundry_node_process" => [] "asic.node" => [] "asic.node_foundry" => [] "blockdiagram" => "/upload/catalog/product/blockdiagram/21403/icon_usb3-x-otg-iip-67b5e00e416a7.png.webp" "category.id" => array:1 [ 0 => 540 ] "category.name" => array:1 [ 0 => "USB 3.2 Controller IP" ] "category.slug" => [] "created_at" => 1739923200 "id" => "21403" "keyfeatures" => "<ul> <li>USB 3.0/3.1/3.2 Common support</li> <ul> <li>Compliant with USB 3.0/3.1/3.2 specification</li> <li>Supports Superspeed USB 3.0, SuperSpeedPlus 3.1, 3.2 </li> <li>Configurable number of Configurations, Interfaces, Alternative Interfaces and Endpoints</li> <li>Configurable PIPE Interface width 8, 16 or 32 bits</li> <li>Supports Low frequency periodic signaling (LFPS) for initialization and power management(U1, U2 & U3)</li> <li>Supports Interrupt/Bulk/Isochronous/Control Transfers</li> <li>Control transfers supported by Endpoint 0</li> <li>Separate Endpoint Buffers for IN bound and OUT bound packets</li> <li>Supports lane polarity inversion</li> <li>Supports extensible Host Controller Interface(xHCI)</li> <li>Supports Scrambler/Descrambler</li> <li>Option to enable/disable scrambling</li> <li>Supports SS Bulk Streaming Endpoints, and USB 2.0 High Bandwidth Interrupt and Isochronous endpoints.</li> <li>Supports configurable endpoint characteristics – for Maximum Packet Size, Endpoint Type etc.</li> <li>CRC32 Checking and generation for SS Data and Header Packets.</li> <li>CRC16 checking and generation for HS/FS/LS data packets.</li> <li>CRC5 generation and checking for Tokens.</li> <li>Supports Split Transfers for FS/LS devices connected to HS Hubs while operating in Embedded Host Mode.</li> <li>Supports preamble for LS transfers while operating in Embedded Host Mode.</li> <li>Supports Protocol Layer Error Handling.</li> <li>Provides prioritized scheduling for periodic endpoints. </li> <li>Separate round robin scheduling algorithm within Periodic and Non-periodic endpoints pipes.</li> <li>Supports USB Suspend state and supports remote wakeup devices.</li> <li>Supports all HS/FS USB Link Power Management States – L1, L2.</li> <li>Supports all SS USB Link Power Management States – U1, U2, and U3.</li> <li>Supports system low power and related system states such as Sleep, Hibernate, Warm/ Cold boot etc.</li> <li>Support for clock gating and multi-power-well support.</li> <li>Supports USB 3.0 Link Power Management</li> <li>Support USB 2.0 LPM transactions.</li> <li>Supports USB 3.0 Loopack and Compliance Mode.</li> <li>Support USB 2.0 Test mode. </li> <li>Configurable number of Downstream ports for Embedded Host Applications. </li> <li>Supports multiple devices connected under SS/HS/FS hub for Embedded Host Applications </li> </ul> <li>USB 3.0</li> <ul> <li>Supports Gen1 super speed with 5GT/s data rate</li> <li>Supports single lane</li> <li>Supports ADP,HNP,SRP and RSP</li> <li>Supports LCRD_A to LCRD_D Credits</li> </ul> <li>USB 3.0 OTG</li> <ul> <li>Supported devices </li> <li>SS-OTG </li> <li>SSPC-OTG Devices </li> <li>SS-PO Devices </li> <li>SS-EH Devices</li> <li>Supported protocols</li> <li>SRP</li> <li>HNP</li> <li>ADP</li> <li>RSP for USB 3.0 </li> <li>Supported speeds</li> <li>SS,HS and FS</li> <li>Supported feature selector</li> <li>b_hnp_enable</li> <li>a_hnp_support</li> <li>a_alt_hnp_support</li> <li>NTF_HOST_REL</li> <li>B3_RSP_ENABLE</li> <li>Support the all timeout condition</li> <li>a_wait_vfall_timout</li> <li>a_wait_vrise_timout </li> <li>a3_polling_tmout</li> <li>a3_recovery_tmout</li> <li>a3_rx_detect_active_tmout</li> <li>rsp_cnf_err_tmout</li> <li>rsp_ack_err_tmout</li> <li>rsp_wrst_err_timout</li> <li>b3_polling_tmout</li> <li>b3_recovery_tmout</li> <li>b3_rx_detect_active_tmout</li> <li>Combination of SSPC-OTG device communication</li> <li>SSPC-OTG device to SSPC-OTG device</li> <li>SSPC-OTG device to SS-OTG device</li> <li>SS-OTG device to SSPC-OTG device </li> </ul> <li>USB 3.1</li> <li>In addition to USB3.0 features,USB3.1 supports the following features</li> <ul> <li>Supports SuperSpeedPlus LFPS Based PWM Message (LBPM)</li> <li>Supports Gen2 with SuperSpeedPlus and Gen1 with Super speed</li> <li>Supports specific LFPS patterns(SCD1/SCD2) for Super speed plus ports</li> <li>Supports SuperSpeedPlus Precision Time Measurement</li> <li>Supports SuperSpeedPlus Transaction Reordering for periodic and asynchronous packet</li> <li>Supports Length field replica</li> <li>Supports Endpoint companion descriptor</li> <li>Supports Type-A and Type-B credits</li> <li>Supports 128B/132B Encoding/Decoding</li> </ul> <li>USB 3.2</li> <li>In addition to USB 3.0 and USB 3.1 features, USB 3.2 supports the following features.</li> <ul> <li>Supports Dual lane</li> <li>Supports Gen2 with SuperSpeedPlus and Gen1 with Super speed</li> <li>Supports Deskew buffer</li> <li>Supports Data striping in dual lanes</li> <li>Supports Configuration summary descriptor</li> <li>Supports link error count and soft error count</li> <li>Supports retimer connectivity models</li> <li>Supports all the Retimer state machine states[RTSM]</li> <li>Supports SRIS and Bit-Level Retimers functionality</li> <li>Supports Retimer presence announcement through LBPM</li> </ul> <li>Support DMA (Optional)</li> <li>Fully synthesizable.</li> <li>Static synchronous design.</li> <li>Positive edge clocking and no internal tri-states.</li> <li>Scan test ready.</li> <li>Simple interface allows easy connection to microprocessor/microcontroller devices</li> </ul>\n" "keyfeatures_cn" => "" "keywords" => "" "logo" => "smartdv2-66bb477aa35f7.webp" "logo2" => "smartdv2-66bb477aa35f7.webp" "name" => "asic.node" "overview" => """ USB3.x OTG interface provides full support for the USB3.x synchronous serial interface, compatible with USB 3.0/3.1/3.2 specification. Through its USB3.x compatibility, it provides a simple interface to a wide range of low-cost devices. USB3.x OTG IIP is proven in FPGA environment. The host interface of the USB3.x OTG can be simple interface or can be AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.\n USB3.x OTG IIP is supported natively in Verilog and VHDL\n """ "overview_cn" => "" "partnumber" => "USB 3.x OTG IIP" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 179 "provider.name" => "SmartDV Technologies" "provider.object" => "{"id":179,"name":"SmartDV Technologies","providerslug":"smartdv-technologies"}" "provider.priority" => 126 "provider.slug" => "smartdv-technologies" "published_as_new_at" => 0 "seofeatures" => """ <ul><li>USB 3.0/3.1/3.2 Common support</li>\n <li>Compliant with USB 3.0/3.1/3.2 specification</li>\n <li>Supports Superspeed USB 3.0, SuperSpeedPlus 3.1, 3.2 </li>\n <li>Configurable number of Configurations, Interfaces, Alternative Interfaces and Endpoints</li></ul> """ "seofeatures_cn" => "" "shortdescription" => "USB3.x OTG IIP\n" "shortdescription_cn" => "" "slug" => "usb3-x-otg-iip-ip" "sortable_id" => 21403 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:1 [ 0 => 7 ] "taxo2" => array:1 [ 0 => 64 ] "taxo3" => array:1 [ 0 => 538 ] "taxo4" => array:1 [ 0 => 540 ] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => """ USB 3.x OTG IIP USB3.x IIP\n SmartDV Technologies """ "text_low_priority" => """ USB3.x OTG interface provides full support for the synchronous serial compatible with USB 3.0/3.1/3.2 specification. Through its compatibility it a simple to wide range of low-cost devices. IIP is proven in FPGA environment. The host can be or AMBA AHB AXI VCI OCP Avalon PLB Tilelink Wishbone Custom protocol.\n USB3.x supported natively Verilog and VHDL\n Common Compliant specification Supports Superspeed 3.0 SuperSpeedPlus 3.1 3.2 Configurable number Configurations Interfaces Alternative Endpoints PIPE Interface width 8 16 32 bits Low frequency periodic signaling (LFPS) initialization power management(U1 U2 & U3) Interrupt/Bulk/Isochronous/Control Transfers Control transfers by Endpoint 0 Separate Buffers IN bound OUT packets lane polarity inversion extensible Host Controller Interface(xHCI) Scrambler/Descrambler Option enable/disable scrambling SS Bulk Streaming 2.0 High Bandwidth Interrupt Isochronous endpoints. configurable endpoint characteristics – Maximum Packet Size Type etc. CRC32 Checking generation Data Header Packets. CRC16 checking HS/FS/LS data packets. CRC5 Tokens. Split FS/LS devices connected HS Hubs while operating Embedded Mode. preamble LS Protocol Layer Error Handling. Provides prioritized scheduling round robin algorithm within Periodic Non-periodic endpoints pipes. Suspend state supports remote wakeup all HS/FS Link Power Management States L1 L2. U1 U3. system low related states such as Sleep Hibernate Warm/ Cold boot Support clock gating multi-power-well support. LPM transactions. Loopack Compliance Test mode. Downstream ports Applications. multiple under SS/HS/FS hub Applications Gen1 super speed 5GT/s rate single ADP HNP SRP RSP LCRD_A LCRD_D Credits Supported SS-OTG SSPC-OTG Devices SS-PO SS-EH protocols speeds FS feature selector b_hnp_enable a_hnp_support a_alt_hnp_support NTF_HOST_REL B3_RSP_ENABLE timeout condition a_wait_vfall_timout a_wait_vrise_timout a3_polling_tmout a3_recovery_tmout a3_rx_detect_active_tmout rsp_cnf_err_tmout rsp_ack_err_tmout rsp_wrst_err_timout b3_polling_tmout b3_recovery_tmout b3_rx_detect_active_tmout Combination device communication In addition USB3.0 features USB3.1 following LFPS Based PWM Message (LBPM) Gen2 Super specific patterns(SCD1/SCD2) plus Precision Time Measurement Transaction Reordering asynchronous packet Length field replica companion descriptor Type-A Type-B credits 128B/132B Encoding/Decoding features. Dual Deskew buffer striping dual lanes Configuration summary link error count soft retimer connectivity models Retimer machine states[RTSM] SRIS Bit-Level Retimers functionality presence announcement through LBPM DMA (Optional) Fully synthesizable. Static design. Positive edge clocking no internal tri-states. Scan test ready. Simple allows easy connection microprocessor/microcontroller \n """ "text_medium_priority" => "" "updated_at" => 1742063898 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ "matched_tokens" => array:1 [ 0 => "OTG" ] "snippet" => """ USB 3.x OTG IIP USB3.x IIP\n SmartDV Technologies """ ] "text_low_priority" => array:2 [ "matched_tokens" => array:1 [ 0 => "OTG" ] "snippet" => "USB3.x OTG interface provides full support" ] ] "highlights" => array:2 [ 0 => array:3 [ "field" => "text_low_priority" "matched_tokens" => array:1 [ 0 => "OTG" ] "snippet" => "USB3.x OTG interface provides full support" ] 1 => array:3 [ "field" => "text_high_priority" "matched_tokens" => array:1 [ 0 => "OTG" ] "snippet" => """ USB 3.x OTG IIP USB3.x IIP\n SmartDV Technologies """ ] ] "text_match" => 1763168118846259202 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1763168118846259202" "tokens_matched" => 3 "typo_prefix_score" => 0 ] ] 3 => array:5 [ "document" => array:48 [ "asic.foundry" => [] "asic.foundry_node" => [] "asic.foundry_node_process" => [] "asic.node" => [] "asic.node_foundry" => [] "blockdiagram" => "" "category.id" => array:1 [ 0 => 97 ] "category.name" => array:1 [ 0 => "USB Controller IP" ] "category.slug" => [] "created_at" => 1741737600 "id" => "22401" "keyfeatures" => "<ul><li>Configurations</li><ul><li> Gen2x2, Gen1x2, Gen2x1, and Gen1x1 </li></ul><li>Supported DUT Models</li><ul><li> Host, Device and PHY Model for USB2 or USB3 </li><li> Hub Model (3.2/3.1/3.0/2.0) </li><li> xHCI Model (Extensible Host Controller Interface) </li><li> Re-timer Model </li><li> Re-driver Model </li></ul><li>Supported Interfaces</li><ul><li> Serial (TX/TX_, RX/RX_) </li><li> DPDM (Dp/Dm) </li><li> HSIC </li><li> UTMI/UTMI+ (MAC or MACRO (include-PHY) with 8 or 16-bit data width) </li><li> ULPI (MAC or MACRO) </li><li> PIPE (MAC, PHY, or MACRO (include-PHY) with 8, 16, or 32-bit PIPE width) </li></ul><li>OTG Support</li><ul><li> OTG 1.3, 2.0, and 3.0 revisions with both A-device and B-device configurations </li></ul><li>OTG Protocol</li><ul><li> SRP, ADP, HNP and RSP </li></ul><li>Framework and Protocol Layer</li><ul><li> Control, Bulk, Isochronous, Interrupt Transfers </li><li> SSI (Smart Isochronous) </li><li> Bulk Streaming </li><li> Data Bursting </li><li> Updates value of Endpoint Companion and Isochronous Endpoint Companion descriptor type </li></ul><li>Physical Layer</li><ul><li> 8b/10b (Gen1x2) and 128b/132b (Gen2x2) encoding/decoding per lane </li><li> Separate clock source per lane </li><li> Spread Spectrum Clocking (SSC) </li><li> Control for SKP and SYNC insertion </li><li> Clock Recovery </li><li> Lane-Lane De-skew on Rx </li><li> LFSR per lane and enable/disable scrambling </li><li> PHY loop-back state with bit error rate test </li><li> Re-timer presence announcement based on LBPM signaling&nbsp; </li><li> Fe-timer SKP number&nbsp;calculation in Host and Device VIP </li></ul><li>Link Layer</li><ul><li> Link Power Management U0, U1, U2, and U3 </li><li> RTSSM and LTSSM with user control to direct into any state </li><li> Nullified and partially nullified DP </li><li> Loopback and Compliance </li><li> Ux Exit on configuration lane </li><li> Speed negotiation and fallback for host, device, hub </li><li> ByPass Link training </li><li> Holding VIP LTSSM until DUT is ready </li></ul><li>Extensible Host Controller Interface</li><ul><li> Support for user control to initialize MMIO and host memory space </li><li> Additional hooks in the TB to connect xHCI driver with PCIE interface </li><li> TRBs (Multi/Single), Command TRB, Event TRB, Transfer TRB, other TRB </li><li> Scatter-Gather Transfers </li><li> Scratchpad buffer </li><li> Command Interface/Ring (Command Ring, Event Ring, Transfer Rung)/Input Context and Device Context </li><li> Supports all types of transactions </li></ul><li>Protocol Traffic</li><ul><li> Supports all types of transfers: bulk, control, interrupt, and isochronous and split transactions </li><li> Full control on the device VIP to do flow control, such as sending NRDY or ERDY </li></ul><li>Loopback and BERT</li><ul><li> PHY loop-back state with bit error rate test </li></ul><li>Hub</li><ul><li> Hub training, basic topology enumeration, packet routing, and forwarding </li><li> USB3.1/3.2 Hub with manual enumeration, basic topologies, training, packet forwarding </li></ul><li>Enumeration</li><ul><li> Bypass the enumeration process and do backdoor register writing for set_address and set_config </li><li> Manual enumeration </li><li> Enable auto enumeration process from the host VIP </li></ul><li>Register Interface</li><ul><li> Change the severity (Error, Warning, Info) of protocol assertions </li><li> Initiate low-power enter/exit sequences from the VIP </li><li> Control functionality such as end-point buffers, to exercise device flow control, streaming </li><li> Collect VIP model information, such as device states, device address, end-point information, LTSSM states, and more. The information can easily accessed in the testbench </li></ul><li>Error Injection</li><ul><li> Predefined error injections such as Crc5, Crc16, and Crc32 for header packets, link commands, data packets, discarding a packet </li><li> Additional Error Injection scenarios can be generated using VIP callbacks </li></ul><li>Tunneling with USB4</li><ul><li> Support for USB4 Interface (USB3 Tunneling)</li></ul>" "keyfeatures_cn" => "" "keywords" => "" "logo" => "tality-66bb475ed438e.webp" "logo2" => "tality-66bb475ed438e.webp" "name" => "asic.node" "overview" => "The Cadence® Verification IP (VIP) for USB is a complete VIP solution for the Universal Serial Bus Revision 3.2 Specification and errata. It provides a mature and comprehensive verification IP (VIP) for the USB protocol, which is part of the USB family. Incorporating the latest protocol updates, the USB VIP is not only a complete bus functional model (BFM) for the DUT but it also provides integrated automatic protocol checks and coverage model. USB VIP is designed to make it easy for you to integrate in testbenches for IP, system-on-chip (SOC), and system level. The USB VIP helps you to reduce time to test by accelerating verification closure and ensuring end product quality.The VIP for USB runs on all major simulators and supports all main verification languages, such as Verilog, System Verilog, and e, alongside industry-standard methodologies for testbench writing, such as Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).Supported Specifications: USB3.2, USB 3.1, USB3.0, USB2, USB1.1 and xHCI." "overview_cn" => "" "partnumber" => "Simulation VIP for USB" "priority" => 1 "priority_taxo" => 0 "productTypes" => array:1 [ 0 => "vip" ] "provider.id" => 24 "provider.name" => "Cadence Design Systems, Inc." "provider.object" => "{"id":24,"name":"Cadence Design Systems, Inc.","providerslug":"cadence-design-systems-inc"}" "provider.priority" => 1501 "provider.slug" => "cadence-design-systems-inc" "published_as_new_at" => 0 "seofeatures" => """ <ul><li>Configurations</li>\n <li> Gen2x2, Gen1x2, Gen2x1, and Gen1x1 </li>\n <li>Supported DUT Models</li>\n <li> Host, Device and PHY Model for USB2 or USB3 </li></ul> """ "seofeatures_cn" => "" "shortdescription" => "Simulation VIP for USB" "shortdescription_cn" => "" "slug" => "simulation-vip-for-usb-ip" "sortable_id" => 22401 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:1 [ 0 => 7 ] "taxo2" => array:1 [ 0 => 64 ] "taxo3" => array:1 [ 0 => 380 ] "taxo4" => array:1 [ 0 => 97 ] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "Simulation VIP for USB Cadence Design Systems Inc." "text_low_priority" => "The Cadence® Verification IP (VIP) for USB is a complete VIP solution the Universal Serial Bus Revision 3.2 Specification and errata. It provides mature comprehensive verification protocol which part of family. Incorporating latest updates not only bus functional model (BFM) DUT but it also integrated automatic checks coverage model. designed to make easy you integrate in testbenches system-on-chip (SOC) system level. helps reduce time test by accelerating closure ensuring end product quality.The runs on all major simulators supports main languages such as Verilog System e alongside industry-standard methodologies testbench writing Methodology (UVM) Open (OVM).Supported Specifications: USB3.2 3.1 USB3.0 USB2 USB1.1 xHCI. Configurations Gen2x2 Gen1x2 Gen2x1 Gen1x1 Supported Models Host Device PHY Model or USB3 Hub (3.2/3.1/3.0/2.0) xHCI (Extensible Controller Interface) Re-timer Re-driver Interfaces (TX/TX_ RX/RX_) DPDM (Dp/Dm) HSIC UTMI/UTMI+ (MAC MACRO (include-PHY) with 8 16-bit data width) ULPI MACRO) PIPE 16 32-bit OTG Support 1.3 2.0 3.0 revisions both A-device B-device configurations Protocol SRP ADP HNP RSP Framework Layer Control Bulk Isochronous Interrupt Transfers SSI (Smart Isochronous) Streaming Data Bursting Updates value Endpoint Companion descriptor type Physical 8b/10b (Gen1x2) 128b/132b (Gen2x2) encoding/decoding per lane Separate clock source Spread Spectrum Clocking (SSC) SKP SYNC insertion Clock Recovery Lane-Lane De-skew Rx LFSR enable/disable scrambling loop-back state bit error rate presence announcement based LBPM signaling&nbsp; Fe-timer number&nbsp;calculation Link Power Management U0 U1 U2 U3 RTSSM LTSSM user control direct into any Nullified partially nullified DP Loopback Compliance Ux Exit configuration Speed negotiation fallback host device hub ByPass training Holding until ready Extensible Interface initialize MMIO memory space Additional hooks TB connect driver PCIE interface TRBs (Multi/Single) Command TRB Event Transfer other Scatter-Gather Scratchpad buffer Interface/Ring (Command Ring Rung)/Input Context Supports types transactions Traffic transfers: bulk interrupt isochronous split Full do flow sending NRDY ERDY BERT basic topology enumeration packet routing forwarding USB3.1/3.2 manual topologies Enumeration Bypass process backdoor register set_address set_config Manual Enable auto from Register Change severity (Error Warning Info) assertions Initiate low-power enter/exit sequences functionality end-point buffers exercise streaming Collect information states address more. can easily accessed Error Injection Predefined injections Crc5 Crc16 Crc32 header packets link commands discarding scenarios be generated using callbacks Tunneling USB4 (USB3 Tunneling)" "text_medium_priority" => "" "updated_at" => 1742108634 ] "highlight" => array:1 [ "text_low_priority" => array:2 [ "matched_tokens" => array:1 [ 0 => "USB3.0" ] "snippet" => "OVM).Supported Specifications: USB3.2 3.1 USB3.0 USB2 USB1.1 xHCI. Configurations" ] ] "highlights" => array:1 [ 0 => array:3 [ "field" => "text_low_priority" "matched_tokens" => array:1 [ 0 => "USB3.0" ] "snippet" => "OVM).Supported Specifications: USB3.2 3.1 USB3.0 USB2 USB1.1 xHCI. Configurations" ] ] "text_match" => 1760916387752050689 "text_match_info" => array:7 [ "best_field_score" => "1116681273344" "best_field_weight" => 14 "fields_matched" => 1 "num_tokens_dropped" => 0 "score" => "1760916387752050689" "tokens_matched" => 3 "typo_prefix_score" => 0 ] ] 4 => array:5 [ "document" => array:48 [ "asic.foundry" => [] "asic.foundry_node" => [] "asic.foundry_node_process" => [] "asic.node" => [] "asic.node_foundry" => [] "blockdiagram" => "/upload/catalog/product/blockdiagram/21401/icon_usb3-x-host-iip-67b5e00db8a06.png.webp" "category.id" => array:1 [ 0 => 540 ] "category.name" => array:1 [ 0 => "USB 3.2 Controller IP" ] "category.slug" => [] "created_at" => 1739923200 "id" => "21401" "keyfeatures" => "<ul> <li>USB 3.0/3.1/3.2 Common support</li> <ul> <li>Compliant with USB 3.0/3.1/3.2 specification</li> <li>Supports Superspeed USB 3.0, SuperSpeedPlus 3.1, 3.2 and 3.0 OTG</li> <li>Configurable number of Configurations, Interfaces, Alternative Interfaces and Endpoints</li> <li>Configurable PIPE Interface width 8, 16 or 32 bits</li> <li>Supports Low frequency periodic signaling (LFPS) for initialization and power management(U1, U2 & U3)</li> <li>Supports Interrupt/Bulk/Isochronous/Control Transfers</li> <li>Control transfers supported by Endpoint 0</li> <li>Separate Endpoint Buffers for IN bound and OUT bound packets</li> <li>Supports lane polarity inversion</li> <li>Supports Bulk Streaming</li> <li>Supports extensible Host Controller Interface(xHCI)</li> <li>Supports Scrambler/Descrambler</li> <li>Option to enable/disable scrambling</li> <li>CRC checking and generation</li> <li>Supports Protocol Layer Error Handling.</li> <li>Provides prioritized scheduling for periodic endpoints.</li> <li>Separate round robin scheduling algorithm within Periodic and Non-periodic endpoints pipes.</li> <li>Supports PTM</li> <li>Implements Type 1 and 2 Buffers</li> <li>Supports LFPS Signaling, SCD/LBPM Messaging</li> <li>Supports Master and Slave Loopback mode for PHY layer testing</li> <li>Supports Compliance mode entry as per specification.</li> <li>Supports USB Suspend state and supports remote wakeup devices.</li> <li>Supports all SS/SSP Link Power Management States – U1, U2, U3</li> <li>Supports all HS/FS USB Link Power Management States – L1, L2.</li> <li>Supports system low power and related system states such as Sleep, Hibernate, Warm/ Cold boot etc.</li> <li>Support for clock gating and multi-power-well support.</li> <li>This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262</li> </ul> <li></li> <li>USB 3.0</li> <ul> <li>Supports Gen1 super speed with 5GT/s data rate</li> <li>Supports single lane</li> <li>Supports ADP,HNP,SRP and RSP</li> <li>Supports LCRD_A to LCRD_D Credits</li> </ul> <li>USB 3.1</li> <li>In addition to USB3.0 features,USB3.1 supports the following features</li> <ul> <li>Supports Gen2 with SuperSpeedPlus and Gen1 with Super speed</li> <li>Supports specific LFPS patterns(SCD1/SCD2) for Super speed plus ports</li> <li>Supports SuperSpeedPlus LFPS Based PWM Message (LBPM)</li> <li>Supports SuperSpeedPlus Precision Time Measurement</li> <li>Supports SuperSpeedPlus Transaction Reordering for periodic and asynchronous packet</li> <li>Supports Length field replica</li> <li>Supports Endpoint companion descriptor</li> <li>Supports Type-A and Type-B credits</li> <li>Supports 128B/132B Encoding/Decoding</li> </ul> <li>USB 3.2</li> <li>In addition to USB3.0 and USB3.1 features, USB 3.2 supports the following features.</li> <ul> <li>Supports Dual lane</li> <li>Supports Gen2 with SuperSpeedPlus and Gen1 with Super speed</li> <li>Supports Deskew buffer</li> <li>Supports Data striping in dual lanes</li> <li>Supports Configuration summary descriptor</li> <li>Supports link error count and soft error count</li> <li>Supports retimer connectivity models</li> <li>Supports all the Retimer state machine states[RTSM]</li> <li>Supports SRIS and Bit-Level Retimers functionality</li> <li>Supports Retimer presence announcement through LBPM</li> </ul> <li>Support DMA (Optional)</li> <li>Fully synthesizable.</li> <li>Static synchronous design.</li> <li>Positive edge clocking and no internal tri-states.</li> <li>Scan test ready.</li> <li>Simple interface allows easy connection to microprocessor/microcontroller devices.</li> </ul>\n" "keyfeatures_cn" => "" "keywords" => "" "logo" => "smartdv2-66bb477aa35f7.webp" "logo2" => "smartdv2-66bb477aa35f7.webp" "name" => "asic.node" "overview" => """ USB3.x Host interface provides full support for the USB3.x synchronous serial interface, compatible with USB 3.0/3.1/3.2 specification. Through its USB compatibility, it provides a simple interface to a wide range of low-cost devices. USB3.x Host IIP is proven in FPGA environment. The host interface of the USB3.x Host can be simple interface or can be AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.\n USB3.x HOST IIP is supported natively in Verilog and VHDL\n """ "overview_cn" => "" "partnumber" => "USB3.x HOST IIP" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 179 "provider.name" => "SmartDV Technologies" "provider.object" => "{"id":179,"name":"SmartDV Technologies","providerslug":"smartdv-technologies"}" "provider.priority" => 126 "provider.slug" => "smartdv-technologies" "published_as_new_at" => 0 "seofeatures" => """ <ul><li>USB 3.0/3.1/3.2 Common support</li>\n <li>Compliant with USB 3.0/3.1/3.2 specification</li>\n <li>Supports Superspeed USB 3.0, SuperSpeedPlus 3.1, 3.2 and 3.0 OTG</li>\n <li>Configurable number of Configurations, Interfaces, Alternative Interfaces and Endpoints</li></ul> """ "seofeatures_cn" => "" "shortdescription" => "USB3.x HOST IIP\n" "shortdescription_cn" => "" "slug" => "usb3-x-host-iip-ip" "sortable_id" => 21401 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:1 [ 0 => 7 ] "taxo2" => array:1 [ 0 => 64 ] "taxo3" => array:1 [ 0 => 538 ] "taxo4" => array:1 [ 0 => 540 ] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => """ USB3.x HOST IIP IIP\n SmartDV Technologies """ "text_low_priority" => """ USB3.x Host interface provides full support for the synchronous serial compatible with USB 3.0/3.1/3.2 specification. Through its compatibility it a simple to wide range of low-cost devices. IIP is proven in FPGA environment. The host can be or AMBA AHB AXI VCI OCP Avalon PLB Tilelink Wishbone Custom protocol.\n USB3.x HOST supported natively Verilog and VHDL\n Common Compliant specification Supports Superspeed 3.0 SuperSpeedPlus 3.1 3.2 OTG Configurable number Configurations Interfaces Alternative Endpoints PIPE Interface width 8 16 32 bits Low frequency periodic signaling (LFPS) initialization power management(U1 U2 & U3) Interrupt/Bulk/Isochronous/Control Transfers Control transfers by Endpoint 0 Separate Buffers IN bound OUT packets lane polarity inversion Bulk Streaming extensible Controller Interface(xHCI) Scrambler/Descrambler Option enable/disable scrambling CRC checking generation Protocol Layer Error Handling. Provides prioritized scheduling endpoints. round robin algorithm within Periodic Non-periodic endpoints pipes. PTM Implements Type 1 2 LFPS Signaling SCD/LBPM Messaging Master Slave Loopback mode PHY layer testing Compliance entry as per Suspend state supports remote wakeup all SS/SSP Link Power Management States – U1 U3 HS/FS L1 L2. system low related states such Sleep Hibernate Warm/ Cold boot etc. Support clock gating multi-power-well support. This core achieves ASIL B made achieve D ISO26262 Gen1 super speed 5GT/s data rate single ADP HNP SRP RSP LCRD_A LCRD_D Credits In addition USB3.0 features USB3.1 following Gen2 Super specific patterns(SCD1/SCD2) plus ports Based PWM Message (LBPM) Precision Time Measurement Transaction Reordering asynchronous packet Length field replica companion descriptor Type-A Type-B credits 128B/132B Encoding/Decoding features. Dual Deskew buffer Data striping dual lanes Configuration summary link error count soft retimer connectivity models Retimer machine states[RTSM] SRIS Bit-Level Retimers functionality presence announcement through LBPM DMA (Optional) Fully synthesizable. Static design. Positive edge clocking no internal tri-states. Scan test ready. Simple allows easy connection microprocessor/microcontroller \n """ "text_medium_priority" => "" "updated_at" => 1742063898 ] "highlight" => array:1 [ "text_low_priority" => array:2 [ "matched_tokens" => array:1 [ 0 => "OTG" ] "snippet" => "3.0 SuperSpeedPlus 3.1 3.2 OTG Configurable number Configurations Interfaces" ] ] "highlights" => array:1 [ 0 => array:3 [ "field" => "text_low_priority" "matched_tokens" => array:1 [ 0 => "OTG" ] "snippet" => "3.0 SuperSpeedPlus 3.1 3.2 OTG Configurable number Configurations Interfaces" ] ] "text_match" => 1760916387752050689 "text_match_info" => array:7 [ "best_field_score" => "1116681273344" "best_field_weight" => 14 "fields_matched" => 1 "num_tokens_dropped" => 0 "score" => "1760916387752050689" "tokens_matched" => 3 "typo_prefix_score" => 0 ] ] ] "out_of" => 18250 "page" => 1 "request_params" => array:4 [ "collection_name" => "product_semiiphub" "first_q" => "USB3.0 OTG controller" "per_page" => 10 "q" => "USB3.0 OTG controller" ] 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interface, support Host, Peripheral and OTG function" "shortdescription_cn" => "" "slug" => "usb3-0-otg-controller-with-axi-interface-support-host-peripheral-and-otg-function" "sortable_id" => 11499 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:1 [ 0 => 7 ] "taxo2" => array:1 [ 0 => 64 ] "taxo3" => array:1 [ 0 => 381 ] "taxo4" => array:1 [ 0 => 324 ] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "FOTG330 USB3.0 OTG controller with AXI interface support Host Peripheral and function Faraday Technology" "text_low_priority" => "USB3.0 OTG controller with AXI interface support Host Peripheral and function" "text_medium_priority" => "" "updated_at" => 1504169416 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ "matched_tokens" => array:3 [ 0 => "USB3.0" 1 => "OTG" 2 => "controller" ] "snippet" => "FOTG330 USB3.0 OTG controller with AXI interface support Host Peripheral and function Faraday Technology" ] "text_low_priority" => array:2 [ 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"asic.foundry_node" => [] "asic.foundry_node_process" => [] "asic.node" => [] "asic.node_foundry" => [] "blockdiagram" => "" "category.id" => array:3 [ 0 => 97 1 => 324 2 => 384 ] "category.name" => array:3 [ 0 => "USB Controller IP" 1 => "USB 3.0 Controller IP" 2 => "USB On-The-Go Controller IP" ] "category.slug" => [] "created_at" => 1385624115 "id" => "5501" "keyfeatures" => "" "keyfeatures_cn" => "" "keywords" => "USB3.0 Superspeed OTG Controller" "logo" => "wwago-66bb4783aec17.webp" "logo2" => "wwago-66bb4783aec17.webp" "name" => "asic.node" "overview" => """ WWAGO USB3.0 SS-OTG controller IP is compliant with OTG&EH3.0. USB3.0 SS-OTG controller is able to dynamically swap host/peripheral roles while operating at SuperSpeed using Role Swapping Protocol (RSP) as defined in OTG&EH3.0 specification. The IP is capable of handling multiple devices when acting as Host. \n \n On-The-Go 3.0 is an upgrade to On-the-Go 2.0 and is backwards compatible with past versions. The Embedded Host supplement adds details on how smart appliances like tablets, phones and even cameras will be able to use a single USB 3.0 port as either a host or peripheral. \n \n With this USB3.0 SuperSpeed OTG core from WWAGO, SOC designers will speed up their SOC design with rich function. """ "overview_cn" => "" "partnumber" => "USB3.0 SS-OTG controller" "priority" => 1 "priority_taxo" => 0 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 229 "provider.name" => "WWAGO Inc." "provider.object" => "{"id":229,"name":"WWAGO Inc.","providerslug":"wwago-inc"}" "provider.priority" => 1 "provider.slug" => "wwago-inc" "published_as_new_at" => 0 "seofeatures" => "" "seofeatures_cn" => "" "shortdescription" => "USB3.0 Superspeed OTG Controller" "shortdescription_cn" => "" "slug" => "usb3-0-superspeed-otg-controller" "sortable_id" => 5501 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:1 [ 0 => 7 ] "taxo2" => array:1 [ 0 => 64 ] "taxo3" => array:3 [ 0 => 380 1 => 381 2 => 383 ] "taxo4" => array:3 [ 0 => 97 1 => 324 2 => 384 ] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "USB3.0 SS-OTG controller Superspeed OTG Controller WWAGO Inc." "text_low_priority" => """ WWAGO USB3.0 SS-OTG controller IP is compliant with OTG&EH3.0. able to dynamically swap host/peripheral roles while operating at SuperSpeed using Role Swapping Protocol (RSP) as defined in OTG&EH3.0 specification. The capable of handling multiple devices when acting Host. \n \n On-The-Go 3.0 an upgrade On-the-Go 2.0 and backwards compatible past versions. Embedded Host supplement adds details on how smart appliances like tablets phones even cameras will be use a single USB port either host or peripheral.\n \n With this OTG core from SOC designers speed up their design rich function. """ "text_medium_priority" => "USB3.0 Superspeed OTG Controller " "updated_at" => 1385693940 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ "matched_tokens" => array:4 [ 0 => "USB3.0" 1 => "controller" 2 => "OTG" 3 => "Controller" ] "snippet" => "USB3.0 SS-OTG controller Superspeed OTG Controller WWAGO Inc." ] "text_low_priority" => array:2 [ "matched_tokens" => array:2 [ 0 => "USB3.0" 1 => "controller" ] "snippet" => "WWAGO USB3.0 SS-OTG controller IP is compliant with" ] ] "highlights" => array:2 [ 0 => array:3 [ "field" => "text_high_priority" "matched_tokens" => array:4 [ 0 => "USB3.0" 1 => "controller" 2 => "OTG" 3 => "Controller" ] "snippet" => "USB3.0 SS-OTG controller Superspeed OTG Controller WWAGO Inc." ] 1 => array:3 [ "field" => "text_low_priority" "matched_tokens" => array:2 [ 0 => "USB3.0" 1 => "controller" ] "snippet" => "WWAGO USB3.0 SS-OTG controller IP is compliant with" ] ] "text_match" => 1763185779749683202 "text_match_info" => array:7 [ "best_field_score" => "3315704266752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1763185779749683202" "tokens_matched" => 3 "typo_prefix_score" => 0 ] ] 2 => array:5 [ "document" => array:48 [ "asic.foundry" => [] "asic.foundry_node" => [] "asic.foundry_node_process" => [] "asic.node" => [] "asic.node_foundry" => [] "blockdiagram" => "/upload/catalog/product/blockdiagram/21403/icon_usb3-x-otg-iip-67b5e00e416a7.png.webp" "category.id" => array:1 [ 0 => 540 ] "category.name" => array:1 [ 0 => "USB 3.2 Controller IP" ] "category.slug" => [] "created_at" => 1739923200 "id" => "21403" "keyfeatures" => "<ul> <li>USB 3.0/3.1/3.2 Common support</li> <ul> <li>Compliant with USB 3.0/3.1/3.2 specification</li> <li>Supports Superspeed USB 3.0, SuperSpeedPlus 3.1, 3.2 </li> <li>Configurable number of Configurations, Interfaces, Alternative Interfaces and Endpoints</li> <li>Configurable PIPE Interface width 8, 16 or 32 bits</li> <li>Supports Low frequency periodic signaling (LFPS) for initialization and power management(U1, U2 & U3)</li> <li>Supports Interrupt/Bulk/Isochronous/Control Transfers</li> <li>Control transfers supported by Endpoint 0</li> <li>Separate Endpoint Buffers for IN bound and OUT bound packets</li> <li>Supports lane polarity inversion</li> <li>Supports extensible Host Controller Interface(xHCI)</li> <li>Supports Scrambler/Descrambler</li> <li>Option to enable/disable scrambling</li> <li>Supports SS Bulk Streaming Endpoints, and USB 2.0 High Bandwidth Interrupt and Isochronous endpoints.</li> <li>Supports configurable endpoint characteristics – for Maximum Packet Size, Endpoint Type etc.</li> <li>CRC32 Checking and generation for SS Data and Header Packets.</li> <li>CRC16 checking and generation for HS/FS/LS data packets.</li> <li>CRC5 generation and checking for Tokens.</li> <li>Supports Split Transfers for FS/LS devices connected to HS Hubs while operating in Embedded Host Mode.</li> <li>Supports preamble for LS transfers while operating in Embedded Host Mode.</li> <li>Supports Protocol Layer Error Handling.</li> <li>Provides prioritized scheduling for periodic endpoints. </li> <li>Separate round robin scheduling algorithm within Periodic and Non-periodic endpoints pipes.</li> <li>Supports USB Suspend state and supports remote wakeup devices.</li> <li>Supports all HS/FS USB Link Power Management States – L1, L2.</li> <li>Supports all SS USB Link Power Management States – U1, U2, and U3.</li> <li>Supports system low power and related system states such as Sleep, Hibernate, Warm/ Cold boot etc.</li> <li>Support for clock gating and multi-power-well support.</li> <li>Supports USB 3.0 Link Power Management</li> <li>Support USB 2.0 LPM transactions.</li> <li>Supports USB 3.0 Loopack and Compliance Mode.</li> <li>Support USB 2.0 Test mode. </li> <li>Configurable number of Downstream ports for Embedded Host Applications. </li> <li>Supports multiple devices connected under SS/HS/FS hub for Embedded Host Applications </li> </ul> <li>USB 3.0</li> <ul> <li>Supports Gen1 super speed with 5GT/s data rate</li> <li>Supports single lane</li> <li>Supports ADP,HNP,SRP and RSP</li> <li>Supports LCRD_A to LCRD_D Credits</li> </ul> <li>USB 3.0 OTG</li> <ul> <li>Supported devices </li> <li>SS-OTG </li> <li>SSPC-OTG Devices </li> <li>SS-PO Devices </li> <li>SS-EH Devices</li> <li>Supported protocols</li> <li>SRP</li> <li>HNP</li> <li>ADP</li> <li>RSP for USB 3.0 </li> <li>Supported speeds</li> <li>SS,HS and FS</li> <li>Supported feature selector</li> <li>b_hnp_enable</li> <li>a_hnp_support</li> <li>a_alt_hnp_support</li> <li>NTF_HOST_REL</li> <li>B3_RSP_ENABLE</li> <li>Support the all timeout condition</li> <li>a_wait_vfall_timout</li> <li>a_wait_vrise_timout </li> <li>a3_polling_tmout</li> <li>a3_recovery_tmout</li> <li>a3_rx_detect_active_tmout</li> <li>rsp_cnf_err_tmout</li> <li>rsp_ack_err_tmout</li> <li>rsp_wrst_err_timout</li> <li>b3_polling_tmout</li> <li>b3_recovery_tmout</li> <li>b3_rx_detect_active_tmout</li> <li>Combination of SSPC-OTG device communication</li> <li>SSPC-OTG device to SSPC-OTG device</li> <li>SSPC-OTG device to SS-OTG device</li> <li>SS-OTG device to SSPC-OTG device </li> </ul> <li>USB 3.1</li> <li>In addition to USB3.0 features,USB3.1 supports the following features</li> <ul> <li>Supports SuperSpeedPlus LFPS Based PWM Message (LBPM)</li> <li>Supports Gen2 with SuperSpeedPlus and Gen1 with Super speed</li> <li>Supports specific LFPS patterns(SCD1/SCD2) for Super speed plus ports</li> <li>Supports SuperSpeedPlus Precision Time Measurement</li> <li>Supports SuperSpeedPlus Transaction Reordering for periodic and asynchronous packet</li> <li>Supports Length field replica</li> <li>Supports Endpoint companion descriptor</li> <li>Supports Type-A and Type-B credits</li> <li>Supports 128B/132B Encoding/Decoding</li> </ul> <li>USB 3.2</li> <li>In addition to USB 3.0 and USB 3.1 features, USB 3.2 supports the following features.</li> <ul> <li>Supports Dual lane</li> <li>Supports Gen2 with SuperSpeedPlus and Gen1 with Super speed</li> <li>Supports Deskew buffer</li> <li>Supports Data striping in dual lanes</li> <li>Supports Configuration summary descriptor</li> <li>Supports link error count and soft error count</li> <li>Supports retimer connectivity models</li> <li>Supports all the Retimer state machine states[RTSM]</li> <li>Supports SRIS and Bit-Level Retimers functionality</li> <li>Supports Retimer presence announcement through LBPM</li> </ul> <li>Support DMA (Optional)</li> <li>Fully synthesizable.</li> <li>Static synchronous design.</li> <li>Positive edge clocking and no internal tri-states.</li> <li>Scan test ready.</li> <li>Simple interface allows easy connection to microprocessor/microcontroller devices</li> </ul>\n" "keyfeatures_cn" => "" "keywords" => "" "logo" => "smartdv2-66bb477aa35f7.webp" "logo2" => "smartdv2-66bb477aa35f7.webp" "name" => "asic.node" "overview" => """ USB3.x OTG interface provides full support for the USB3.x synchronous serial interface, compatible with USB 3.0/3.1/3.2 specification. Through its USB3.x compatibility, it provides a simple interface to a wide range of low-cost devices. USB3.x OTG IIP is proven in FPGA environment. The host interface of the USB3.x OTG can be simple interface or can be AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.\n USB3.x OTG IIP is supported natively in Verilog and VHDL\n """ "overview_cn" => "" "partnumber" => "USB 3.x OTG IIP" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 179 "provider.name" => "SmartDV Technologies" "provider.object" => "{"id":179,"name":"SmartDV Technologies","providerslug":"smartdv-technologies"}" "provider.priority" => 126 "provider.slug" => "smartdv-technologies" "published_as_new_at" => 0 "seofeatures" => """ <ul><li>USB 3.0/3.1/3.2 Common support</li>\n <li>Compliant with USB 3.0/3.1/3.2 specification</li>\n <li>Supports Superspeed USB 3.0, SuperSpeedPlus 3.1, 3.2 </li>\n <li>Configurable number of Configurations, Interfaces, Alternative Interfaces and Endpoints</li></ul> """ "seofeatures_cn" => "" "shortdescription" => "USB3.x OTG IIP\n" "shortdescription_cn" => "" "slug" => "usb3-x-otg-iip-ip" "sortable_id" => 21403 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:1 [ 0 => 7 ] "taxo2" => array:1 [ 0 => 64 ] "taxo3" => array:1 [ 0 => 538 ] "taxo4" => array:1 [ 0 => 540 ] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => """ USB 3.x OTG IIP USB3.x IIP\n SmartDV Technologies """ "text_low_priority" => """ USB3.x OTG interface provides full support for the synchronous serial compatible with USB 3.0/3.1/3.2 specification. Through its compatibility it a simple to wide range of low-cost devices. IIP is proven in FPGA environment. The host can be or AMBA AHB AXI VCI OCP Avalon PLB Tilelink Wishbone Custom protocol.\n USB3.x supported natively Verilog and VHDL\n Common Compliant specification Supports Superspeed 3.0 SuperSpeedPlus 3.1 3.2 Configurable number Configurations Interfaces Alternative Endpoints PIPE Interface width 8 16 32 bits Low frequency periodic signaling (LFPS) initialization power management(U1 U2 & U3) Interrupt/Bulk/Isochronous/Control Transfers Control transfers by Endpoint 0 Separate Buffers IN bound OUT packets lane polarity inversion extensible Host Controller Interface(xHCI) Scrambler/Descrambler Option enable/disable scrambling SS Bulk Streaming 2.0 High Bandwidth Interrupt Isochronous endpoints. configurable endpoint characteristics – Maximum Packet Size Type etc. CRC32 Checking generation Data Header Packets. CRC16 checking HS/FS/LS data packets. CRC5 Tokens. Split FS/LS devices connected HS Hubs while operating Embedded Mode. preamble LS Protocol Layer Error Handling. Provides prioritized scheduling round robin algorithm within Periodic Non-periodic endpoints pipes. Suspend state supports remote wakeup all HS/FS Link Power Management States L1 L2. U1 U3. system low related states such as Sleep Hibernate Warm/ Cold boot Support clock gating multi-power-well support. LPM transactions. Loopack Compliance Test mode. Downstream ports Applications. multiple under SS/HS/FS hub Applications Gen1 super speed 5GT/s rate single ADP HNP SRP RSP LCRD_A LCRD_D Credits Supported SS-OTG SSPC-OTG Devices SS-PO SS-EH protocols speeds FS feature selector b_hnp_enable a_hnp_support a_alt_hnp_support NTF_HOST_REL B3_RSP_ENABLE timeout condition a_wait_vfall_timout a_wait_vrise_timout a3_polling_tmout a3_recovery_tmout a3_rx_detect_active_tmout rsp_cnf_err_tmout rsp_ack_err_tmout rsp_wrst_err_timout b3_polling_tmout b3_recovery_tmout b3_rx_detect_active_tmout Combination device communication In addition USB3.0 features USB3.1 following LFPS Based PWM Message (LBPM) Gen2 Super specific patterns(SCD1/SCD2) plus Precision Time Measurement Transaction Reordering asynchronous packet Length field replica companion descriptor Type-A Type-B credits 128B/132B Encoding/Decoding features. Dual Deskew buffer striping dual lanes Configuration summary link error count soft retimer connectivity models Retimer machine states[RTSM] SRIS Bit-Level Retimers functionality presence announcement through LBPM DMA (Optional) Fully synthesizable. Static design. Positive edge clocking no internal tri-states. Scan test ready. Simple allows easy connection microprocessor/microcontroller \n """ "text_medium_priority" => "" "updated_at" => 1742063898 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ "matched_tokens" => array:1 [ 0 => "OTG" ] "snippet" => """ USB 3.x OTG IIP USB3.x IIP\n SmartDV Technologies """ ] "text_low_priority" => array:2 [ "matched_tokens" => array:1 [ 0 => "OTG" ] "snippet" => "USB3.x OTG interface provides full support" ] ] "highlights" => array:2 [ 0 => array:3 [ "field" => "text_low_priority" "matched_tokens" => array:1 [ 0 => "OTG" ] "snippet" => "USB3.x OTG interface provides full support" ] 1 => array:3 [ "field" => "text_high_priority" "matched_tokens" => array:1 [ 0 => "OTG" ] "snippet" => """ USB 3.x OTG IIP USB3.x IIP\n SmartDV Technologies """ ] ] "text_match" => 1763168118846259202 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1763168118846259202" "tokens_matched" => 3 "typo_prefix_score" => 0 ] ] 3 => array:5 [ "document" => array:48 [ "asic.foundry" => [] "asic.foundry_node" => [] "asic.foundry_node_process" => [] "asic.node" => [] "asic.node_foundry" => [] "blockdiagram" => "" "category.id" => array:1 [ 0 => 97 ] "category.name" => array:1 [ 0 => "USB Controller IP" ] "category.slug" => [] "created_at" => 1741737600 "id" => "22401" "keyfeatures" => "<ul><li>Configurations</li><ul><li> Gen2x2, Gen1x2, Gen2x1, and Gen1x1 </li></ul><li>Supported DUT Models</li><ul><li> Host, Device and PHY Model for USB2 or USB3 </li><li> Hub Model (3.2/3.1/3.0/2.0) </li><li> xHCI Model (Extensible Host Controller Interface) </li><li> Re-timer Model </li><li> Re-driver Model </li></ul><li>Supported Interfaces</li><ul><li> Serial (TX/TX_, RX/RX_) </li><li> DPDM (Dp/Dm) </li><li> HSIC </li><li> UTMI/UTMI+ (MAC or MACRO (include-PHY) with 8 or 16-bit data width) </li><li> ULPI (MAC or MACRO) </li><li> PIPE (MAC, PHY, or MACRO (include-PHY) with 8, 16, or 32-bit PIPE width) </li></ul><li>OTG Support</li><ul><li> OTG 1.3, 2.0, and 3.0 revisions with both A-device and B-device configurations </li></ul><li>OTG Protocol</li><ul><li> SRP, ADP, HNP and RSP </li></ul><li>Framework and Protocol Layer</li><ul><li> Control, Bulk, Isochronous, Interrupt Transfers </li><li> SSI (Smart Isochronous) </li><li> Bulk Streaming </li><li> Data Bursting </li><li> Updates value of Endpoint Companion and Isochronous Endpoint Companion descriptor type </li></ul><li>Physical Layer</li><ul><li> 8b/10b (Gen1x2) and 128b/132b (Gen2x2) encoding/decoding per lane </li><li> Separate clock source per lane </li><li> Spread Spectrum Clocking (SSC) </li><li> Control for SKP and SYNC insertion </li><li> Clock Recovery </li><li> Lane-Lane De-skew on Rx </li><li> LFSR per lane and enable/disable scrambling </li><li> PHY loop-back state with bit error rate test </li><li> Re-timer presence announcement based on LBPM signaling&nbsp; </li><li> Fe-timer SKP number&nbsp;calculation in Host and Device VIP </li></ul><li>Link Layer</li><ul><li> Link Power Management U0, U1, U2, and U3 </li><li> RTSSM and LTSSM with user control to direct into any state </li><li> Nullified and partially nullified DP </li><li> Loopback and Compliance </li><li> Ux Exit on configuration lane </li><li> Speed negotiation and fallback for host, device, hub </li><li> ByPass Link training </li><li> Holding VIP LTSSM until DUT is ready </li></ul><li>Extensible Host Controller Interface</li><ul><li> Support for user control to initialize MMIO and host memory space </li><li> Additional hooks in the TB to connect xHCI driver with PCIE interface </li><li> TRBs (Multi/Single), Command TRB, Event TRB, Transfer TRB, other TRB </li><li> Scatter-Gather Transfers </li><li> Scratchpad buffer </li><li> Command Interface/Ring (Command Ring, Event Ring, Transfer Rung)/Input Context and Device Context </li><li> Supports all types of transactions </li></ul><li>Protocol Traffic</li><ul><li> Supports all types of transfers: bulk, control, interrupt, and isochronous and split transactions </li><li> Full control on the device VIP to do flow control, such as sending NRDY or ERDY </li></ul><li>Loopback and BERT</li><ul><li> PHY loop-back state with bit error rate test </li></ul><li>Hub</li><ul><li> Hub training, basic topology enumeration, packet routing, and forwarding </li><li> USB3.1/3.2 Hub with manual enumeration, basic topologies, training, packet forwarding </li></ul><li>Enumeration</li><ul><li> Bypass the enumeration process and do backdoor register writing for set_address and set_config </li><li> Manual enumeration </li><li> Enable auto enumeration process from the host VIP </li></ul><li>Register Interface</li><ul><li> Change the severity (Error, Warning, Info) of protocol assertions </li><li> Initiate low-power enter/exit sequences from the VIP </li><li> Control functionality such as end-point buffers, to exercise device flow control, streaming </li><li> Collect VIP model information, such as device states, device address, end-point information, LTSSM states, and more. The information can easily accessed in the testbench </li></ul><li>Error Injection</li><ul><li> Predefined error injections such as Crc5, Crc16, and Crc32 for header packets, link commands, data packets, discarding a packet </li><li> Additional Error Injection scenarios can be generated using VIP callbacks </li></ul><li>Tunneling with USB4</li><ul><li> Support for USB4 Interface (USB3 Tunneling)</li></ul>" "keyfeatures_cn" => "" "keywords" => "" "logo" => "tality-66bb475ed438e.webp" "logo2" => "tality-66bb475ed438e.webp" "name" => "asic.node" "overview" => "The Cadence® Verification IP (VIP) for USB is a complete VIP solution for the Universal Serial Bus Revision 3.2 Specification and errata. It provides a mature and comprehensive verification IP (VIP) for the USB protocol, which is part of the USB family. Incorporating the latest protocol updates, the USB VIP is not only a complete bus functional model (BFM) for the DUT but it also provides integrated automatic protocol checks and coverage model. USB VIP is designed to make it easy for you to integrate in testbenches for IP, system-on-chip (SOC), and system level. The USB VIP helps you to reduce time to test by accelerating verification closure and ensuring end product quality.The VIP for USB runs on all major simulators and supports all main verification languages, such as Verilog, System Verilog, and e, alongside industry-standard methodologies for testbench writing, such as Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).Supported Specifications: USB3.2, USB 3.1, USB3.0, USB2, USB1.1 and xHCI." "overview_cn" => "" "partnumber" => "Simulation VIP for USB" "priority" => 1 "priority_taxo" => 0 "productTypes" => array:1 [ 0 => "vip" ] "provider.id" => 24 "provider.name" => "Cadence Design Systems, Inc." "provider.object" => "{"id":24,"name":"Cadence Design Systems, Inc.","providerslug":"cadence-design-systems-inc"}" "provider.priority" => 1501 "provider.slug" => "cadence-design-systems-inc" "published_as_new_at" => 0 "seofeatures" => """ <ul><li>Configurations</li>\n <li> Gen2x2, Gen1x2, Gen2x1, and Gen1x1 </li>\n <li>Supported DUT Models</li>\n <li> Host, Device and PHY Model for USB2 or USB3 </li></ul> """ "seofeatures_cn" => "" "shortdescription" => "Simulation VIP for USB" "shortdescription_cn" => "" "slug" => "simulation-vip-for-usb-ip" "sortable_id" => 22401 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:1 [ 0 => 7 ] "taxo2" => array:1 [ 0 => 64 ] "taxo3" => array:1 [ 0 => 380 ] "taxo4" => array:1 [ 0 => 97 ] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "Simulation VIP for USB Cadence Design Systems Inc." "text_low_priority" => "The Cadence® Verification IP (VIP) for USB is a complete VIP solution the Universal Serial Bus Revision 3.2 Specification and errata. It provides mature comprehensive verification protocol which part of family. Incorporating latest updates not only bus functional model (BFM) DUT but it also integrated automatic checks coverage model. designed to make easy you integrate in testbenches system-on-chip (SOC) system level. helps reduce time test by accelerating closure ensuring end product quality.The runs on all major simulators supports main languages such as Verilog System e alongside industry-standard methodologies testbench writing Methodology (UVM) Open (OVM).Supported Specifications: USB3.2 3.1 USB3.0 USB2 USB1.1 xHCI. Configurations Gen2x2 Gen1x2 Gen2x1 Gen1x1 Supported Models Host Device PHY Model or USB3 Hub (3.2/3.1/3.0/2.0) xHCI (Extensible Controller Interface) Re-timer Re-driver Interfaces (TX/TX_ RX/RX_) DPDM (Dp/Dm) HSIC UTMI/UTMI+ (MAC MACRO (include-PHY) with 8 16-bit data width) ULPI MACRO) PIPE 16 32-bit OTG Support 1.3 2.0 3.0 revisions both A-device B-device configurations Protocol SRP ADP HNP RSP Framework Layer Control Bulk Isochronous Interrupt Transfers SSI (Smart Isochronous) Streaming Data Bursting Updates value Endpoint Companion descriptor type Physical 8b/10b (Gen1x2) 128b/132b (Gen2x2) encoding/decoding per lane Separate clock source Spread Spectrum Clocking (SSC) SKP SYNC insertion Clock Recovery Lane-Lane De-skew Rx LFSR enable/disable scrambling loop-back state bit error rate presence announcement based LBPM signaling&nbsp; Fe-timer number&nbsp;calculation Link Power Management U0 U1 U2 U3 RTSSM LTSSM user control direct into any Nullified partially nullified DP Loopback Compliance Ux Exit configuration Speed negotiation fallback host device hub ByPass training Holding until ready Extensible Interface initialize MMIO memory space Additional hooks TB connect driver PCIE interface TRBs (Multi/Single) Command TRB Event Transfer other Scatter-Gather Scratchpad buffer Interface/Ring (Command Ring Rung)/Input Context Supports types transactions Traffic transfers: bulk interrupt isochronous split Full do flow sending NRDY ERDY BERT basic topology enumeration packet routing forwarding USB3.1/3.2 manual topologies Enumeration Bypass process backdoor register set_address set_config Manual Enable auto from Register Change severity (Error Warning Info) assertions Initiate low-power enter/exit sequences functionality end-point buffers exercise streaming Collect information states address more. can easily accessed Error Injection Predefined injections Crc5 Crc16 Crc32 header packets link commands discarding scenarios be generated using callbacks Tunneling USB4 (USB3 Tunneling)" "text_medium_priority" => "" "updated_at" => 1742108634 ] "highlight" => array:1 [ "text_low_priority" => array:2 [ "matched_tokens" => array:1 [ 0 => "USB3.0" ] "snippet" => "OVM).Supported Specifications: USB3.2 3.1 USB3.0 USB2 USB1.1 xHCI. Configurations" ] ] "highlights" => array:1 [ 0 => array:3 [ "field" => "text_low_priority" "matched_tokens" => array:1 [ 0 => "USB3.0" ] "snippet" => "OVM).Supported Specifications: USB3.2 3.1 USB3.0 USB2 USB1.1 xHCI. Configurations" ] ] "text_match" => 1760916387752050689 "text_match_info" => array:7 [ "best_field_score" => "1116681273344" "best_field_weight" => 14 "fields_matched" => 1 "num_tokens_dropped" => 0 "score" => "1760916387752050689" "tokens_matched" => 3 "typo_prefix_score" => 0 ] ] 4 => array:5 [ "document" => array:48 [ "asic.foundry" => [] "asic.foundry_node" => [] "asic.foundry_node_process" => [] "asic.node" => [] "asic.node_foundry" => [] "blockdiagram" => "/upload/catalog/product/blockdiagram/21401/icon_usb3-x-host-iip-67b5e00db8a06.png.webp" "category.id" => array:1 [ 0 => 540 ] "category.name" => array:1 [ 0 => "USB 3.2 Controller IP" ] "category.slug" => [] "created_at" => 1739923200 "id" => "21401" "keyfeatures" => "<ul> <li>USB 3.0/3.1/3.2 Common support</li> <ul> <li>Compliant with USB 3.0/3.1/3.2 specification</li> <li>Supports Superspeed USB 3.0, SuperSpeedPlus 3.1, 3.2 and 3.0 OTG</li> <li>Configurable number of Configurations, Interfaces, Alternative Interfaces and Endpoints</li> <li>Configurable PIPE Interface width 8, 16 or 32 bits</li> <li>Supports Low frequency periodic signaling (LFPS) for initialization and power management(U1, U2 & U3)</li> <li>Supports Interrupt/Bulk/Isochronous/Control Transfers</li> <li>Control transfers supported by Endpoint 0</li> <li>Separate Endpoint Buffers for IN bound and OUT bound packets</li> <li>Supports lane polarity inversion</li> <li>Supports Bulk Streaming</li> <li>Supports extensible Host Controller Interface(xHCI)</li> <li>Supports Scrambler/Descrambler</li> <li>Option to enable/disable scrambling</li> <li>CRC checking and generation</li> <li>Supports Protocol Layer Error Handling.</li> <li>Provides prioritized scheduling for periodic endpoints.</li> <li>Separate round robin scheduling algorithm within Periodic and Non-periodic endpoints pipes.</li> <li>Supports PTM</li> <li>Implements Type 1 and 2 Buffers</li> <li>Supports LFPS Signaling, SCD/LBPM Messaging</li> <li>Supports Master and Slave Loopback mode for PHY layer testing</li> <li>Supports Compliance mode entry as per specification.</li> <li>Supports USB Suspend state and supports remote wakeup devices.</li> <li>Supports all SS/SSP Link Power Management States – U1, U2, U3</li> <li>Supports all HS/FS USB Link Power Management States – L1, L2.</li> <li>Supports system low power and related system states such as Sleep, Hibernate, Warm/ Cold boot etc.</li> <li>Support for clock gating and multi-power-well support.</li> <li>This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262</li> </ul> <li></li> <li>USB 3.0</li> <ul> <li>Supports Gen1 super speed with 5GT/s data rate</li> <li>Supports single lane</li> <li>Supports ADP,HNP,SRP and RSP</li> <li>Supports LCRD_A to LCRD_D Credits</li> </ul> <li>USB 3.1</li> <li>In addition to USB3.0 features,USB3.1 supports the following features</li> <ul> <li>Supports Gen2 with SuperSpeedPlus and Gen1 with Super speed</li> <li>Supports specific LFPS patterns(SCD1/SCD2) for Super speed plus ports</li> <li>Supports SuperSpeedPlus LFPS Based PWM Message (LBPM)</li> <li>Supports SuperSpeedPlus Precision Time Measurement</li> <li>Supports SuperSpeedPlus Transaction Reordering for periodic and asynchronous packet</li> <li>Supports Length field replica</li> <li>Supports Endpoint companion descriptor</li> <li>Supports Type-A and Type-B credits</li> <li>Supports 128B/132B Encoding/Decoding</li> </ul> <li>USB 3.2</li> <li>In addition to USB3.0 and USB3.1 features, USB 3.2 supports the following features.</li> <ul> <li>Supports Dual lane</li> <li>Supports Gen2 with SuperSpeedPlus and Gen1 with Super speed</li> <li>Supports Deskew buffer</li> <li>Supports Data striping in dual lanes</li> <li>Supports Configuration summary descriptor</li> <li>Supports link error count and soft error count</li> <li>Supports retimer connectivity models</li> <li>Supports all the Retimer state machine states[RTSM]</li> <li>Supports SRIS and Bit-Level Retimers functionality</li> <li>Supports Retimer presence announcement through LBPM</li> </ul> <li>Support DMA (Optional)</li> <li>Fully synthesizable.</li> <li>Static synchronous design.</li> <li>Positive edge clocking and no internal tri-states.</li> <li>Scan test ready.</li> <li>Simple interface allows easy connection to microprocessor/microcontroller devices.</li> </ul>\n" "keyfeatures_cn" => "" "keywords" => "" "logo" => "smartdv2-66bb477aa35f7.webp" "logo2" => "smartdv2-66bb477aa35f7.webp" "name" => "asic.node" "overview" => """ USB3.x Host interface provides full support for the USB3.x synchronous serial interface, compatible with USB 3.0/3.1/3.2 specification. Through its USB compatibility, it provides a simple interface to a wide range of low-cost devices. USB3.x Host IIP is proven in FPGA environment. The host interface of the USB3.x Host can be simple interface or can be AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.\n USB3.x HOST IIP is supported natively in Verilog and VHDL\n """ "overview_cn" => "" "partnumber" => "USB3.x HOST IIP" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 179 "provider.name" => "SmartDV Technologies" "provider.object" => "{"id":179,"name":"SmartDV Technologies","providerslug":"smartdv-technologies"}" "provider.priority" => 126 "provider.slug" => "smartdv-technologies" "published_as_new_at" => 0 "seofeatures" => """ <ul><li>USB 3.0/3.1/3.2 Common support</li>\n <li>Compliant with USB 3.0/3.1/3.2 specification</li>\n <li>Supports Superspeed USB 3.0, SuperSpeedPlus 3.1, 3.2 and 3.0 OTG</li>\n <li>Configurable number of Configurations, Interfaces, Alternative Interfaces and Endpoints</li></ul> """ "seofeatures_cn" => "" "shortdescription" => "USB3.x HOST IIP\n" "shortdescription_cn" => "" "slug" => "usb3-x-host-iip-ip" "sortable_id" => 21401 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:1 [ 0 => 7 ] "taxo2" => array:1 [ 0 => 64 ] "taxo3" => array:1 [ 0 => 538 ] "taxo4" => array:1 [ 0 => 540 ] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => """ USB3.x HOST IIP IIP\n SmartDV Technologies """ "text_low_priority" => """ USB3.x Host interface provides full support for the synchronous serial compatible with USB 3.0/3.1/3.2 specification. Through its compatibility it a simple to wide range of low-cost devices. IIP is proven in FPGA environment. The host can be or AMBA AHB AXI VCI OCP Avalon PLB Tilelink Wishbone Custom protocol.\n USB3.x HOST supported natively Verilog and VHDL\n Common Compliant specification Supports Superspeed 3.0 SuperSpeedPlus 3.1 3.2 OTG Configurable number Configurations Interfaces Alternative Endpoints PIPE Interface width 8 16 32 bits Low frequency periodic signaling (LFPS) initialization power management(U1 U2 & U3) Interrupt/Bulk/Isochronous/Control Transfers Control transfers by Endpoint 0 Separate Buffers IN bound OUT packets lane polarity inversion Bulk Streaming extensible Controller Interface(xHCI) Scrambler/Descrambler Option enable/disable scrambling CRC checking generation Protocol Layer Error Handling. Provides prioritized scheduling endpoints. round robin algorithm within Periodic Non-periodic endpoints pipes. PTM Implements Type 1 2 LFPS Signaling SCD/LBPM Messaging Master Slave Loopback mode PHY layer testing Compliance entry as per Suspend state supports remote wakeup all SS/SSP Link Power Management States – U1 U3 HS/FS L1 L2. system low related states such Sleep Hibernate Warm/ Cold boot etc. Support clock gating multi-power-well support. This core achieves ASIL B made achieve D ISO26262 Gen1 super speed 5GT/s data rate single ADP HNP SRP RSP LCRD_A LCRD_D Credits In addition USB3.0 features USB3.1 following Gen2 Super specific patterns(SCD1/SCD2) plus ports Based PWM Message (LBPM) Precision Time Measurement Transaction Reordering asynchronous packet Length field replica companion descriptor Type-A Type-B credits 128B/132B Encoding/Decoding features. Dual Deskew buffer Data striping dual lanes Configuration summary link error count soft retimer connectivity models Retimer machine states[RTSM] SRIS Bit-Level Retimers functionality presence announcement through LBPM DMA (Optional) Fully synthesizable. Static design. Positive edge clocking no internal tri-states. Scan test ready. Simple allows easy connection microprocessor/microcontroller \n """ "text_medium_priority" => "" "updated_at" => 1742063898 ] "highlight" => array:1 [ "text_low_priority" => array:2 [ "matched_tokens" => array:1 [ 0 => "OTG" ] "snippet" => "3.0 SuperSpeedPlus 3.1 3.2 OTG Configurable number Configurations Interfaces" ] ] "highlights" => array:1 [ 0 => array:3 [ "field" => "text_low_priority" "matched_tokens" => array:1 [ 0 => "OTG" ] "snippet" => "3.0 SuperSpeedPlus 3.1 3.2 OTG Configurable number Configurations Interfaces" ] ] "text_match" => 1760916387752050689 "text_match_info" => array:7 [ "best_field_score" => "1116681273344" "best_field_weight" => 14 "fields_matched" => 1 "num_tokens_dropped" => 0 "score" => "1760916387752050689" "tokens_matched" => 3 "typo_prefix_score" => 0 ] ] ] "out_of" => 18250 "page" => 1 "request_params" => array:4 [ "collection_name" => "product_semiiphub" "first_q" => "USB3.0 OTG controller" "per_page" => 10 "q" => "USB3.0 OTG controller" ] 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"asic.foundry_node" => [] "asic.foundry_node_process" => [] "asic.node" => [] "asic.node_foundry" => [] "blockdiagram" => "" "category.id" => array:3 [ 0 => 97 1 => 324 2 => 384 ] "category.name" => array:3 [ 0 => "USB Controller IP" 1 => "USB 3.0 Controller IP" 2 => "USB On-The-Go Controller IP" ] "category.slug" => [] "created_at" => 1385624115 "id" => "5501" "keyfeatures" => "" "keyfeatures_cn" => "" "keywords" => "USB3.0 Superspeed OTG Controller" "logo" => "wwago-66bb4783aec17.webp" "logo2" => "wwago-66bb4783aec17.webp" "name" => "asic.node" "overview" => """ WWAGO USB3.0 SS-OTG controller IP is compliant with OTG&EH3.0. USB3.0 SS-OTG controller is able to dynamically swap host/peripheral roles while operating at SuperSpeed using Role Swapping Protocol (RSP) as defined in OTG&EH3.0 specification. The IP is capable of handling multiple devices when acting as Host. \n \n On-The-Go 3.0 is an upgrade to On-the-Go 2.0 and is backwards compatible with past versions. The Embedded Host supplement adds details on how smart appliances like tablets, phones and even cameras will be able to use a single USB 3.0 port as either a host or peripheral. \n \n With this USB3.0 SuperSpeed OTG core from WWAGO, SOC designers will speed up their SOC design with rich function. """ "overview_cn" => "" "partnumber" => "USB3.0 SS-OTG controller" "priority" => 1 "priority_taxo" => 0 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 229 "provider.name" => "WWAGO Inc." "provider.object" => "{"id":229,"name":"WWAGO Inc.","providerslug":"wwago-inc"}" "provider.priority" => 1 "provider.slug" => "wwago-inc" "published_as_new_at" => 0 "seofeatures" => "" "seofeatures_cn" => "" "shortdescription" => "USB3.0 Superspeed OTG Controller" "shortdescription_cn" => "" "slug" => "usb3-0-superspeed-otg-controller" "sortable_id" => 5501 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:1 [ 0 => 7 ] "taxo2" => array:1 [ 0 => 64 ] "taxo3" => array:3 [ 0 => 380 1 => 381 2 => 383 ] "taxo4" => array:3 [ 0 => 97 1 => 324 2 => 384 ] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "USB3.0 SS-OTG controller Superspeed OTG Controller WWAGO Inc." "text_low_priority" => """ WWAGO USB3.0 SS-OTG controller IP is compliant with OTG&EH3.0. able to dynamically swap host/peripheral roles while operating at SuperSpeed using Role Swapping Protocol (RSP) as defined in OTG&EH3.0 specification. The capable of handling multiple devices when acting Host. \n \n On-The-Go 3.0 an upgrade On-the-Go 2.0 and backwards compatible past versions. Embedded Host supplement adds details on how smart appliances like tablets phones even cameras will be use a single USB port either host or peripheral.\n \n With this OTG core from SOC designers speed up their design rich function. """ "text_medium_priority" => "USB3.0 Superspeed OTG Controller " "updated_at" => 1385693940 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ "matched_tokens" => array:4 [ 0 => "USB3.0" 1 => "controller" 2 => "OTG" 3 => "Controller" ] "snippet" => "USB3.0 SS-OTG controller Superspeed OTG Controller WWAGO Inc." ] "text_low_priority" => array:2 [ "matched_tokens" => array:2 [ 0 => "USB3.0" 1 => "controller" ] "snippet" => "WWAGO USB3.0 SS-OTG controller IP is compliant with" ] ] "highlights" => array:2 [ 0 => array:3 [ "field" => "text_high_priority" "matched_tokens" => array:4 [ 0 => "USB3.0" 1 => "controller" 2 => "OTG" 3 => "Controller" ] "snippet" => "USB3.0 SS-OTG controller Superspeed OTG Controller WWAGO Inc." ] 1 => array:3 [ "field" => "text_low_priority" "matched_tokens" => array:2 [ 0 => "USB3.0" 1 => "controller" ] "snippet" => "WWAGO USB3.0 SS-OTG controller IP is compliant with" ] ] "text_match" => 1763185779749683202 "text_match_info" => array:7 [ "best_field_score" => "3315704266752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1763185779749683202" "tokens_matched" => 3 "typo_prefix_score" => 0 ] ] 2 => array:5 [ "document" => array:48 [ "asic.foundry" => [] "asic.foundry_node" => [] "asic.foundry_node_process" => [] "asic.node" => [] "asic.node_foundry" => [] "blockdiagram" => "/upload/catalog/product/blockdiagram/21403/icon_usb3-x-otg-iip-67b5e00e416a7.png.webp" "category.id" => array:1 [ 0 => 540 ] "category.name" => array:1 [ 0 => "USB 3.2 Controller IP" ] "category.slug" => [] "created_at" => 1739923200 "id" => "21403" "keyfeatures" => "<ul> <li>USB 3.0/3.1/3.2 Common support</li> <ul> <li>Compliant with USB 3.0/3.1/3.2 specification</li> <li>Supports Superspeed USB 3.0, SuperSpeedPlus 3.1, 3.2 </li> <li>Configurable number of Configurations, Interfaces, Alternative Interfaces and Endpoints</li> <li>Configurable PIPE Interface width 8, 16 or 32 bits</li> <li>Supports Low frequency periodic signaling (LFPS) for initialization and power management(U1, U2 & U3)</li> <li>Supports Interrupt/Bulk/Isochronous/Control Transfers</li> <li>Control transfers supported by Endpoint 0</li> <li>Separate Endpoint Buffers for IN bound and OUT bound packets</li> <li>Supports lane polarity inversion</li> <li>Supports extensible Host Controller Interface(xHCI)</li> <li>Supports Scrambler/Descrambler</li> <li>Option to enable/disable scrambling</li> <li>Supports SS Bulk Streaming Endpoints, and USB 2.0 High Bandwidth Interrupt and Isochronous endpoints.</li> <li>Supports configurable endpoint characteristics – for Maximum Packet Size, Endpoint Type etc.</li> <li>CRC32 Checking and generation for SS Data and Header Packets.</li> <li>CRC16 checking and generation for HS/FS/LS data packets.</li> <li>CRC5 generation and checking for Tokens.</li> <li>Supports Split Transfers for FS/LS devices connected to HS Hubs while operating in Embedded Host Mode.</li> <li>Supports preamble for LS transfers while operating in Embedded Host Mode.</li> <li>Supports Protocol Layer Error Handling.</li> <li>Provides prioritized scheduling for periodic endpoints. </li> <li>Separate round robin scheduling algorithm within Periodic and Non-periodic endpoints pipes.</li> <li>Supports USB Suspend state and supports remote wakeup devices.</li> <li>Supports all HS/FS USB Link Power Management States – L1, L2.</li> <li>Supports all SS USB Link Power Management States – U1, U2, and U3.</li> <li>Supports system low power and related system states such as Sleep, Hibernate, Warm/ Cold boot etc.</li> <li>Support for clock gating and multi-power-well support.</li> <li>Supports USB 3.0 Link Power Management</li> <li>Support USB 2.0 LPM transactions.</li> <li>Supports USB 3.0 Loopack and Compliance Mode.</li> <li>Support USB 2.0 Test mode. </li> <li>Configurable number of Downstream ports for Embedded Host Applications. </li> <li>Supports multiple devices connected under SS/HS/FS hub for Embedded Host Applications </li> </ul> <li>USB 3.0</li> <ul> <li>Supports Gen1 super speed with 5GT/s data rate</li> <li>Supports single lane</li> <li>Supports ADP,HNP,SRP and RSP</li> <li>Supports LCRD_A to LCRD_D Credits</li> </ul> <li>USB 3.0 OTG</li> <ul> <li>Supported devices </li> <li>SS-OTG </li> <li>SSPC-OTG Devices </li> <li>SS-PO Devices </li> <li>SS-EH Devices</li> <li>Supported protocols</li> <li>SRP</li> <li>HNP</li> <li>ADP</li> <li>RSP for USB 3.0 </li> <li>Supported speeds</li> <li>SS,HS and FS</li> <li>Supported feature selector</li> <li>b_hnp_enable</li> <li>a_hnp_support</li> <li>a_alt_hnp_support</li> <li>NTF_HOST_REL</li> <li>B3_RSP_ENABLE</li> <li>Support the all timeout condition</li> <li>a_wait_vfall_timout</li> <li>a_wait_vrise_timout </li> <li>a3_polling_tmout</li> <li>a3_recovery_tmout</li> <li>a3_rx_detect_active_tmout</li> <li>rsp_cnf_err_tmout</li> <li>rsp_ack_err_tmout</li> <li>rsp_wrst_err_timout</li> <li>b3_polling_tmout</li> <li>b3_recovery_tmout</li> <li>b3_rx_detect_active_tmout</li> <li>Combination of SSPC-OTG device communication</li> <li>SSPC-OTG device to SSPC-OTG device</li> <li>SSPC-OTG device to SS-OTG device</li> <li>SS-OTG device to SSPC-OTG device </li> </ul> <li>USB 3.1</li> <li>In addition to USB3.0 features,USB3.1 supports the following features</li> <ul> <li>Supports SuperSpeedPlus LFPS Based PWM Message (LBPM)</li> <li>Supports Gen2 with SuperSpeedPlus and Gen1 with Super speed</li> <li>Supports specific LFPS patterns(SCD1/SCD2) for Super speed plus ports</li> <li>Supports SuperSpeedPlus Precision Time Measurement</li> <li>Supports SuperSpeedPlus Transaction Reordering for periodic and asynchronous packet</li> <li>Supports Length field replica</li> <li>Supports Endpoint companion descriptor</li> <li>Supports Type-A and Type-B credits</li> <li>Supports 128B/132B Encoding/Decoding</li> </ul> <li>USB 3.2</li> <li>In addition to USB 3.0 and USB 3.1 features, USB 3.2 supports the following features.</li> <ul> <li>Supports Dual lane</li> <li>Supports Gen2 with SuperSpeedPlus and Gen1 with Super speed</li> <li>Supports Deskew buffer</li> <li>Supports Data striping in dual lanes</li> <li>Supports Configuration summary descriptor</li> <li>Supports link error count and soft error count</li> <li>Supports retimer connectivity models</li> <li>Supports all the Retimer state machine states[RTSM]</li> <li>Supports SRIS and Bit-Level Retimers functionality</li> <li>Supports Retimer presence announcement through LBPM</li> </ul> <li>Support DMA (Optional)</li> <li>Fully synthesizable.</li> <li>Static synchronous design.</li> <li>Positive edge clocking and no internal tri-states.</li> <li>Scan test ready.</li> <li>Simple interface allows easy connection to microprocessor/microcontroller devices</li> </ul>\n" "keyfeatures_cn" => "" "keywords" => "" "logo" => "smartdv2-66bb477aa35f7.webp" "logo2" => "smartdv2-66bb477aa35f7.webp" "name" => "asic.node" "overview" => """ USB3.x OTG interface provides full support for the USB3.x synchronous serial interface, compatible with USB 3.0/3.1/3.2 specification. Through its USB3.x compatibility, it provides a simple interface to a wide range of low-cost devices. USB3.x OTG IIP is proven in FPGA environment. The host interface of the USB3.x OTG can be simple interface or can be AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.\n USB3.x OTG IIP is supported natively in Verilog and VHDL\n """ "overview_cn" => "" "partnumber" => "USB 3.x OTG IIP" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 179 "provider.name" => "SmartDV Technologies" "provider.object" => "{"id":179,"name":"SmartDV Technologies","providerslug":"smartdv-technologies"}" "provider.priority" => 126 "provider.slug" => "smartdv-technologies" "published_as_new_at" => 0 "seofeatures" => """ <ul><li>USB 3.0/3.1/3.2 Common support</li>\n <li>Compliant with USB 3.0/3.1/3.2 specification</li>\n <li>Supports Superspeed USB 3.0, SuperSpeedPlus 3.1, 3.2 </li>\n <li>Configurable number of Configurations, Interfaces, Alternative Interfaces and Endpoints</li></ul> """ "seofeatures_cn" => "" "shortdescription" => "USB3.x OTG IIP\n" "shortdescription_cn" => "" "slug" => "usb3-x-otg-iip-ip" "sortable_id" => 21403 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:1 [ 0 => 7 ] "taxo2" => array:1 [ 0 => 64 ] "taxo3" => array:1 [ 0 => 538 ] "taxo4" => array:1 [ 0 => 540 ] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => """ USB 3.x OTG IIP USB3.x IIP\n SmartDV Technologies """ "text_low_priority" => """ USB3.x OTG interface provides full support for the synchronous serial compatible with USB 3.0/3.1/3.2 specification. Through its compatibility it a simple to wide range of low-cost devices. IIP is proven in FPGA environment. The host can be or AMBA AHB AXI VCI OCP Avalon PLB Tilelink Wishbone Custom protocol.\n USB3.x supported natively Verilog and VHDL\n Common Compliant specification Supports Superspeed 3.0 SuperSpeedPlus 3.1 3.2 Configurable number Configurations Interfaces Alternative Endpoints PIPE Interface width 8 16 32 bits Low frequency periodic signaling (LFPS) initialization power management(U1 U2 & U3) Interrupt/Bulk/Isochronous/Control Transfers Control transfers by Endpoint 0 Separate Buffers IN bound OUT packets lane polarity inversion extensible Host Controller Interface(xHCI) Scrambler/Descrambler Option enable/disable scrambling SS Bulk Streaming 2.0 High Bandwidth Interrupt Isochronous endpoints. configurable endpoint characteristics – Maximum Packet Size Type etc. CRC32 Checking generation Data Header Packets. CRC16 checking HS/FS/LS data packets. CRC5 Tokens. Split FS/LS devices connected HS Hubs while operating Embedded Mode. preamble LS Protocol Layer Error Handling. Provides prioritized scheduling round robin algorithm within Periodic Non-periodic endpoints pipes. Suspend state supports remote wakeup all HS/FS Link Power Management States L1 L2. U1 U3. system low related states such as Sleep Hibernate Warm/ Cold boot Support clock gating multi-power-well support. LPM transactions. Loopack Compliance Test mode. Downstream ports Applications. multiple under SS/HS/FS hub Applications Gen1 super speed 5GT/s rate single ADP HNP SRP RSP LCRD_A LCRD_D Credits Supported SS-OTG SSPC-OTG Devices SS-PO SS-EH protocols speeds FS feature selector b_hnp_enable a_hnp_support a_alt_hnp_support NTF_HOST_REL B3_RSP_ENABLE timeout condition a_wait_vfall_timout a_wait_vrise_timout a3_polling_tmout a3_recovery_tmout a3_rx_detect_active_tmout rsp_cnf_err_tmout rsp_ack_err_tmout rsp_wrst_err_timout b3_polling_tmout b3_recovery_tmout b3_rx_detect_active_tmout Combination device communication In addition USB3.0 features USB3.1 following LFPS Based PWM Message (LBPM) Gen2 Super specific patterns(SCD1/SCD2) plus Precision Time Measurement Transaction Reordering asynchronous packet Length field replica companion descriptor Type-A Type-B credits 128B/132B Encoding/Decoding features. Dual Deskew buffer striping dual lanes Configuration summary link error count soft retimer connectivity models Retimer machine states[RTSM] SRIS Bit-Level Retimers functionality presence announcement through LBPM DMA (Optional) Fully synthesizable. Static design. Positive edge clocking no internal tri-states. Scan test ready. Simple allows easy connection microprocessor/microcontroller \n """ "text_medium_priority" => "" "updated_at" => 1742063898 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ "matched_tokens" => array:1 [ 0 => "OTG" ] "snippet" => """ USB 3.x OTG IIP USB3.x IIP\n SmartDV Technologies """ ] "text_low_priority" => array:2 [ "matched_tokens" => array:1 [ 0 => "OTG" ] "snippet" => "USB3.x OTG interface provides full support" ] ] "highlights" => array:2 [ 0 => array:3 [ "field" => "text_low_priority" "matched_tokens" => array:1 [ 0 => "OTG" ] "snippet" => "USB3.x OTG interface provides full support" ] 1 => array:3 [ "field" => "text_high_priority" "matched_tokens" => array:1 [ 0 => "OTG" ] "snippet" => """ USB 3.x OTG IIP USB3.x IIP\n SmartDV Technologies """ ] ] "text_match" => 1763168118846259202 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1763168118846259202" "tokens_matched" => 3 "typo_prefix_score" => 0 ] ] 3 => array:5 [ "document" => array:48 [ "asic.foundry" => [] "asic.foundry_node" => [] "asic.foundry_node_process" => [] "asic.node" => [] "asic.node_foundry" => [] "blockdiagram" => "" "category.id" => array:1 [ 0 => 97 ] "category.name" => array:1 [ 0 => "USB Controller IP" ] "category.slug" => [] "created_at" => 1741737600 "id" => "22401" "keyfeatures" => "<ul><li>Configurations</li><ul><li> Gen2x2, Gen1x2, Gen2x1, and Gen1x1 </li></ul><li>Supported DUT Models</li><ul><li> Host, Device and PHY Model for USB2 or USB3 </li><li> Hub Model (3.2/3.1/3.0/2.0) </li><li> xHCI Model (Extensible Host Controller Interface) </li><li> Re-timer Model </li><li> Re-driver Model </li></ul><li>Supported Interfaces</li><ul><li> Serial (TX/TX_, RX/RX_) </li><li> DPDM (Dp/Dm) </li><li> HSIC </li><li> UTMI/UTMI+ (MAC or MACRO (include-PHY) with 8 or 16-bit data width) </li><li> ULPI (MAC or MACRO) </li><li> PIPE (MAC, PHY, or MACRO (include-PHY) with 8, 16, or 32-bit PIPE width) </li></ul><li>OTG Support</li><ul><li> OTG 1.3, 2.0, and 3.0 revisions with both A-device and B-device configurations </li></ul><li>OTG Protocol</li><ul><li> SRP, ADP, HNP and RSP </li></ul><li>Framework and Protocol Layer</li><ul><li> Control, Bulk, Isochronous, Interrupt Transfers </li><li> SSI (Smart Isochronous) </li><li> Bulk Streaming </li><li> Data Bursting </li><li> Updates value of Endpoint Companion and Isochronous Endpoint Companion descriptor type </li></ul><li>Physical Layer</li><ul><li> 8b/10b (Gen1x2) and 128b/132b (Gen2x2) encoding/decoding per lane </li><li> Separate clock source per lane </li><li> Spread Spectrum Clocking (SSC) </li><li> Control for SKP and SYNC insertion </li><li> Clock Recovery </li><li> Lane-Lane De-skew on Rx </li><li> LFSR per lane and enable/disable scrambling </li><li> PHY loop-back state with bit error rate test </li><li> Re-timer presence announcement based on LBPM signaling&nbsp; </li><li> Fe-timer SKP number&nbsp;calculation in Host and Device VIP </li></ul><li>Link Layer</li><ul><li> Link Power Management U0, U1, U2, and U3 </li><li> RTSSM and LTSSM with user control to direct into any state </li><li> Nullified and partially nullified DP </li><li> Loopback and Compliance </li><li> Ux Exit on configuration lane </li><li> Speed negotiation and fallback for host, device, hub </li><li> ByPass Link training </li><li> Holding VIP LTSSM until DUT is ready </li></ul><li>Extensible Host Controller Interface</li><ul><li> Support for user control to initialize MMIO and host memory space </li><li> Additional hooks in the TB to connect xHCI driver with PCIE interface </li><li> TRBs (Multi/Single), Command TRB, Event TRB, Transfer TRB, other TRB </li><li> Scatter-Gather Transfers </li><li> Scratchpad buffer </li><li> Command Interface/Ring (Command Ring, Event Ring, Transfer Rung)/Input Context and Device Context </li><li> Supports all types of transactions </li></ul><li>Protocol Traffic</li><ul><li> Supports all types of transfers: bulk, control, interrupt, and isochronous and split transactions </li><li> Full control on the device VIP to do flow control, such as sending NRDY or ERDY </li></ul><li>Loopback and BERT</li><ul><li> PHY loop-back state with bit error rate test </li></ul><li>Hub</li><ul><li> Hub training, basic topology enumeration, packet routing, and forwarding </li><li> USB3.1/3.2 Hub with manual enumeration, basic topologies, training, packet forwarding </li></ul><li>Enumeration</li><ul><li> Bypass the enumeration process and do backdoor register writing for set_address and set_config </li><li> Manual enumeration </li><li> Enable auto enumeration process from the host VIP </li></ul><li>Register Interface</li><ul><li> Change the severity (Error, Warning, Info) of protocol assertions </li><li> Initiate low-power enter/exit sequences from the VIP </li><li> Control functionality such as end-point buffers, to exercise device flow control, streaming </li><li> Collect VIP model information, such as device states, device address, end-point information, LTSSM states, and more. The information can easily accessed in the testbench </li></ul><li>Error Injection</li><ul><li> Predefined error injections such as Crc5, Crc16, and Crc32 for header packets, link commands, data packets, discarding a packet </li><li> Additional Error Injection scenarios can be generated using VIP callbacks </li></ul><li>Tunneling with USB4</li><ul><li> Support for USB4 Interface (USB3 Tunneling)</li></ul>" "keyfeatures_cn" => "" "keywords" => "" "logo" => "tality-66bb475ed438e.webp" "logo2" => "tality-66bb475ed438e.webp" "name" => "asic.node" "overview" => "The Cadence® Verification IP (VIP) for USB is a complete VIP solution for the Universal Serial Bus Revision 3.2 Specification and errata. It provides a mature and comprehensive verification IP (VIP) for the USB protocol, which is part of the USB family. Incorporating the latest protocol updates, the USB VIP is not only a complete bus functional model (BFM) for the DUT but it also provides integrated automatic protocol checks and coverage model. USB VIP is designed to make it easy for you to integrate in testbenches for IP, system-on-chip (SOC), and system level. The USB VIP helps you to reduce time to test by accelerating verification closure and ensuring end product quality.The VIP for USB runs on all major simulators and supports all main verification languages, such as Verilog, System Verilog, and e, alongside industry-standard methodologies for testbench writing, such as Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).Supported Specifications: USB3.2, USB 3.1, USB3.0, USB2, USB1.1 and xHCI." "overview_cn" => "" "partnumber" => "Simulation VIP for USB" "priority" => 1 "priority_taxo" => 0 "productTypes" => array:1 [ 0 => "vip" ] "provider.id" => 24 "provider.name" => "Cadence Design Systems, Inc." "provider.object" => "{"id":24,"name":"Cadence Design Systems, Inc.","providerslug":"cadence-design-systems-inc"}" "provider.priority" => 1501 "provider.slug" => "cadence-design-systems-inc" "published_as_new_at" => 0 "seofeatures" => """ <ul><li>Configurations</li>\n <li> Gen2x2, Gen1x2, Gen2x1, and Gen1x1 </li>\n <li>Supported DUT Models</li>\n <li> Host, Device and PHY Model for USB2 or USB3 </li></ul> """ "seofeatures_cn" => "" "shortdescription" => "Simulation VIP for USB" "shortdescription_cn" => "" "slug" => "simulation-vip-for-usb-ip" "sortable_id" => 22401 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:1 [ 0 => 7 ] "taxo2" => array:1 [ 0 => 64 ] "taxo3" => array:1 [ 0 => 380 ] "taxo4" => array:1 [ 0 => 97 ] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "Simulation VIP for USB Cadence Design Systems Inc." "text_low_priority" => "The Cadence® Verification IP (VIP) for USB is a complete VIP solution the Universal Serial Bus Revision 3.2 Specification and errata. It provides mature comprehensive verification protocol which part of family. Incorporating latest updates not only bus functional model (BFM) DUT but it also integrated automatic checks coverage model. designed to make easy you integrate in testbenches system-on-chip (SOC) system level. helps reduce time test by accelerating closure ensuring end product quality.The runs on all major simulators supports main languages such as Verilog System e alongside industry-standard methodologies testbench writing Methodology (UVM) Open (OVM).Supported Specifications: USB3.2 3.1 USB3.0 USB2 USB1.1 xHCI. Configurations Gen2x2 Gen1x2 Gen2x1 Gen1x1 Supported Models Host Device PHY Model or USB3 Hub (3.2/3.1/3.0/2.0) xHCI (Extensible Controller Interface) Re-timer Re-driver Interfaces (TX/TX_ RX/RX_) DPDM (Dp/Dm) HSIC UTMI/UTMI+ (MAC MACRO (include-PHY) with 8 16-bit data width) ULPI MACRO) PIPE 16 32-bit OTG Support 1.3 2.0 3.0 revisions both A-device B-device configurations Protocol SRP ADP HNP RSP Framework Layer Control Bulk Isochronous Interrupt Transfers SSI (Smart Isochronous) Streaming Data Bursting Updates value Endpoint Companion descriptor type Physical 8b/10b (Gen1x2) 128b/132b (Gen2x2) encoding/decoding per lane Separate clock source Spread Spectrum Clocking (SSC) SKP SYNC insertion Clock Recovery Lane-Lane De-skew Rx LFSR enable/disable scrambling loop-back state bit error rate presence announcement based LBPM signaling&nbsp; Fe-timer number&nbsp;calculation Link Power Management U0 U1 U2 U3 RTSSM LTSSM user control direct into any Nullified partially nullified DP Loopback Compliance Ux Exit configuration Speed negotiation fallback host device hub ByPass training Holding until ready Extensible Interface initialize MMIO memory space Additional hooks TB connect driver PCIE interface TRBs (Multi/Single) Command TRB Event Transfer other Scatter-Gather Scratchpad buffer Interface/Ring (Command Ring Rung)/Input Context Supports types transactions Traffic transfers: bulk interrupt isochronous split Full do flow sending NRDY ERDY BERT basic topology enumeration packet routing forwarding USB3.1/3.2 manual topologies Enumeration Bypass process backdoor register set_address set_config Manual Enable auto from Register Change severity (Error Warning Info) assertions Initiate low-power enter/exit sequences functionality end-point buffers exercise streaming Collect information states address more. can easily accessed Error Injection Predefined injections Crc5 Crc16 Crc32 header packets link commands discarding scenarios be generated using callbacks Tunneling USB4 (USB3 Tunneling)" "text_medium_priority" => "" "updated_at" => 1742108634 ] "highlight" => array:1 [ "text_low_priority" => array:2 [ "matched_tokens" => array:1 [ 0 => "USB3.0" ] "snippet" => "OVM).Supported Specifications: USB3.2 3.1 USB3.0 USB2 USB1.1 xHCI. Configurations" ] ] "highlights" => array:1 [ 0 => array:3 [ "field" => "text_low_priority" "matched_tokens" => array:1 [ 0 => "USB3.0" ] "snippet" => "OVM).Supported Specifications: USB3.2 3.1 USB3.0 USB2 USB1.1 xHCI. Configurations" ] ] "text_match" => 1760916387752050689 "text_match_info" => array:7 [ "best_field_score" => "1116681273344" "best_field_weight" => 14 "fields_matched" => 1 "num_tokens_dropped" => 0 "score" => "1760916387752050689" "tokens_matched" => 3 "typo_prefix_score" => 0 ] ] 4 => array:5 [ "document" => array:48 [ "asic.foundry" => [] "asic.foundry_node" => [] "asic.foundry_node_process" => [] "asic.node" => [] "asic.node_foundry" => [] "blockdiagram" => "/upload/catalog/product/blockdiagram/21401/icon_usb3-x-host-iip-67b5e00db8a06.png.webp" "category.id" => array:1 [ 0 => 540 ] "category.name" => array:1 [ 0 => "USB 3.2 Controller IP" ] "category.slug" => [] "created_at" => 1739923200 "id" => "21401" "keyfeatures" => "<ul> <li>USB 3.0/3.1/3.2 Common support</li> <ul> <li>Compliant with USB 3.0/3.1/3.2 specification</li> <li>Supports Superspeed USB 3.0, SuperSpeedPlus 3.1, 3.2 and 3.0 OTG</li> <li>Configurable number of Configurations, Interfaces, Alternative Interfaces and Endpoints</li> <li>Configurable PIPE Interface width 8, 16 or 32 bits</li> <li>Supports Low frequency periodic signaling (LFPS) for initialization and power management(U1, U2 & U3)</li> <li>Supports Interrupt/Bulk/Isochronous/Control Transfers</li> <li>Control transfers supported by Endpoint 0</li> <li>Separate Endpoint Buffers for IN bound and OUT bound packets</li> <li>Supports lane polarity inversion</li> <li>Supports Bulk Streaming</li> <li>Supports extensible Host Controller Interface(xHCI)</li> <li>Supports Scrambler/Descrambler</li> <li>Option to enable/disable scrambling</li> <li>CRC checking and generation</li> <li>Supports Protocol Layer Error Handling.</li> <li>Provides prioritized scheduling for periodic endpoints.</li> <li>Separate round robin scheduling algorithm within Periodic and Non-periodic endpoints pipes.</li> <li>Supports PTM</li> <li>Implements Type 1 and 2 Buffers</li> <li>Supports LFPS Signaling, SCD/LBPM Messaging</li> <li>Supports Master and Slave Loopback mode for PHY layer testing</li> <li>Supports Compliance mode entry as per specification.</li> <li>Supports USB Suspend state and supports remote wakeup devices.</li> <li>Supports all SS/SSP Link Power Management States – U1, U2, U3</li> <li>Supports all HS/FS USB Link Power Management States – L1, L2.</li> <li>Supports system low power and related system states such as Sleep, Hibernate, Warm/ Cold boot etc.</li> <li>Support for clock gating and multi-power-well support.</li> <li>This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262</li> </ul> <li></li> <li>USB 3.0</li> <ul> <li>Supports Gen1 super speed with 5GT/s data rate</li> <li>Supports single lane</li> <li>Supports ADP,HNP,SRP and RSP</li> <li>Supports LCRD_A to LCRD_D Credits</li> </ul> <li>USB 3.1</li> <li>In addition to USB3.0 features,USB3.1 supports the following features</li> <ul> <li>Supports Gen2 with SuperSpeedPlus and Gen1 with Super speed</li> <li>Supports specific LFPS patterns(SCD1/SCD2) for Super speed plus ports</li> <li>Supports SuperSpeedPlus LFPS Based PWM Message (LBPM)</li> <li>Supports SuperSpeedPlus Precision Time Measurement</li> <li>Supports SuperSpeedPlus Transaction Reordering for periodic and asynchronous packet</li> <li>Supports Length field replica</li> <li>Supports Endpoint companion descriptor</li> <li>Supports Type-A and Type-B credits</li> <li>Supports 128B/132B Encoding/Decoding</li> </ul> <li>USB 3.2</li> <li>In addition to USB3.0 and USB3.1 features, USB 3.2 supports the following features.</li> <ul> <li>Supports Dual lane</li> <li>Supports Gen2 with SuperSpeedPlus and Gen1 with Super speed</li> <li>Supports Deskew buffer</li> <li>Supports Data striping in dual lanes</li> <li>Supports Configuration summary descriptor</li> <li>Supports link error count and soft error count</li> <li>Supports retimer connectivity models</li> <li>Supports all the Retimer state machine states[RTSM]</li> <li>Supports SRIS and Bit-Level Retimers functionality</li> <li>Supports Retimer presence announcement through LBPM</li> </ul> <li>Support DMA (Optional)</li> <li>Fully synthesizable.</li> <li>Static synchronous design.</li> <li>Positive edge clocking and no internal tri-states.</li> <li>Scan test ready.</li> <li>Simple interface allows easy connection to microprocessor/microcontroller devices.</li> </ul>\n" "keyfeatures_cn" => "" "keywords" => "" "logo" => "smartdv2-66bb477aa35f7.webp" "logo2" => "smartdv2-66bb477aa35f7.webp" "name" => "asic.node" "overview" => """ USB3.x Host interface provides full support for the USB3.x synchronous serial interface, compatible with USB 3.0/3.1/3.2 specification. Through its USB compatibility, it provides a simple interface to a wide range of low-cost devices. USB3.x Host IIP is proven in FPGA environment. The host interface of the USB3.x Host can be simple interface or can be AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.\n USB3.x HOST IIP is supported natively in Verilog and VHDL\n """ "overview_cn" => "" "partnumber" => "USB3.x HOST IIP" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 179 "provider.name" => "SmartDV Technologies" "provider.object" => "{"id":179,"name":"SmartDV Technologies","providerslug":"smartdv-technologies"}" "provider.priority" => 126 "provider.slug" => "smartdv-technologies" "published_as_new_at" => 0 "seofeatures" => """ <ul><li>USB 3.0/3.1/3.2 Common support</li>\n <li>Compliant with USB 3.0/3.1/3.2 specification</li>\n <li>Supports Superspeed USB 3.0, SuperSpeedPlus 3.1, 3.2 and 3.0 OTG</li>\n <li>Configurable number of Configurations, Interfaces, Alternative Interfaces and Endpoints</li></ul> """ "seofeatures_cn" => "" "shortdescription" => "USB3.x HOST IIP\n" "shortdescription_cn" => "" "slug" => "usb3-x-host-iip-ip" "sortable_id" => 21401 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:1 [ 0 => 7 ] "taxo2" => array:1 [ 0 => 64 ] "taxo3" => array:1 [ 0 => 538 ] "taxo4" => array:1 [ 0 => 540 ] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => """ USB3.x HOST IIP IIP\n SmartDV Technologies """ "text_low_priority" => """ USB3.x Host interface provides full support for the synchronous serial compatible with USB 3.0/3.1/3.2 specification. Through its compatibility it a simple to wide range of low-cost devices. IIP is proven in FPGA environment. The host can be or AMBA AHB AXI VCI OCP Avalon PLB Tilelink Wishbone Custom protocol.\n USB3.x HOST supported natively Verilog and VHDL\n Common Compliant specification Supports Superspeed 3.0 SuperSpeedPlus 3.1 3.2 OTG Configurable number Configurations Interfaces Alternative Endpoints PIPE Interface width 8 16 32 bits Low frequency periodic signaling (LFPS) initialization power management(U1 U2 & U3) Interrupt/Bulk/Isochronous/Control Transfers Control transfers by Endpoint 0 Separate Buffers IN bound OUT packets lane polarity inversion Bulk Streaming extensible Controller Interface(xHCI) Scrambler/Descrambler Option enable/disable scrambling CRC checking generation Protocol Layer Error Handling. Provides prioritized scheduling endpoints. round robin algorithm within Periodic Non-periodic endpoints pipes. PTM Implements Type 1 2 LFPS Signaling SCD/LBPM Messaging Master Slave Loopback mode PHY layer testing Compliance entry as per Suspend state supports remote wakeup all SS/SSP Link Power Management States – U1 U3 HS/FS L1 L2. system low related states such Sleep Hibernate Warm/ Cold boot etc. Support clock gating multi-power-well support. This core achieves ASIL B made achieve D ISO26262 Gen1 super speed 5GT/s data rate single ADP HNP SRP RSP LCRD_A LCRD_D Credits In addition USB3.0 features USB3.1 following Gen2 Super specific patterns(SCD1/SCD2) plus ports Based PWM Message (LBPM) Precision Time Measurement Transaction Reordering asynchronous packet Length field replica companion descriptor Type-A Type-B credits 128B/132B Encoding/Decoding features. Dual Deskew buffer Data striping dual lanes Configuration summary link error count soft retimer connectivity models Retimer machine states[RTSM] SRIS Bit-Level Retimers functionality presence announcement through LBPM DMA (Optional) Fully synthesizable. Static design. Positive edge clocking no internal tri-states. Scan test ready. Simple allows easy connection microprocessor/microcontroller \n """ "text_medium_priority" => "" "updated_at" => 1742063898 ] "highlight" => array:1 [ "text_low_priority" => array:2 [ "matched_tokens" => array:1 [ 0 => "OTG" ] "snippet" => "3.0 SuperSpeedPlus 3.1 3.2 OTG Configurable number Configurations Interfaces" ] ] "highlights" => array:1 [ 0 => array:3 [ "field" => "text_low_priority" "matched_tokens" => array:1 [ 0 => "OTG" ] "snippet" => "3.0 SuperSpeedPlus 3.1 3.2 OTG Configurable number Configurations Interfaces" ] ] "text_match" => 1760916387752050689 "text_match_info" => array:7 [ "best_field_score" => "1116681273344" "best_field_weight" => 14 "fields_matched" => 1 "num_tokens_dropped" => 0 "score" => "1760916387752050689" "tokens_matched" => 3 "typo_prefix_score" => 0 ] ] ] "out_of" => 18250 "page" => 1 "request_params" => array:4 [ "collection_name" => "product_semiiphub" "first_q" => "USB3.0 OTG controller" "per_page" => 10 "q" => "USB3.0 OTG controller" ] "search_cutoff" => false "search_time_ms" => 1 ] ]]

USB3.0 OTG controller IP

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Compare 5 IP from 4 vendors (1 - 5)

USB3.0 OTG controller with AXI interface, support Host, Peripheral and OTG function
USB3.0 Superspeed OTG Controller
USB3.x OTG IIP
- USB 3.0/3.1/3.2 Common support
- Compliant with USB 3.0/3.1/3.2 specification
- Supports Superspeed USB 3.0, SuperSpeedPlus 3.1, 3.2
- Configurable number of Configurations, Interfaces, Alternative Interfaces and Endpoints
Simulation VIP for USB
- Configurations
- Gen2x2, Gen1x2, Gen2x1, and Gen1x1
- Supported DUT Models
- Host, Device and PHY Model for USB2 or USB3
USB3.x HOST IIP
- USB 3.0/3.1/3.2 Common support
- Compliant with USB 3.0/3.1/3.2 specification
- Supports Superspeed USB 3.0, SuperSpeedPlus 3.1, 3.2 and 3.0 OTG
- Configurable number of Configurations, Interfaces, Alternative Interfaces and Endpoints