UHS-II PHY IP
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UHS-II PHY Core IP
- The UHS-II PHY IP is a comprehensive, silicon-proven configurable core that has been ported to multiple process nodes and leading foundries.
- It uses sub-LVDS signaling consisting of one pair each for transmit, receive, and an additional reference clock. This low-pin interface has reduced power consumption and low EMI.
- To further reduce power, the reference clock operates at 1/15 or 1/30 of the data transfer speed.
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SD4.x UHSII
- Fully compliant with UHSII specification Ver. 4.x
- Bidirectional receiver/transmitter (2 channels) supporting both full and half duplex modes
- Supports data rates from 390Mbps to 1.56Gbps/ch
- RCLK frequency: 26 to 56MHz
- Built-in PLL and clock recovery
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SD4.1 UHS- II PHY IP
- SD 4.1 compliant SDHC/SDXC UHS-II Physical Layer for Host
- 16bit interface to Link layer
- Supports both Full Duplex mode and Half Duplex mode
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SD UHS2 PHY & Controller
- DTI SD host controller facilitates host equipment to communicate with SD card.
- It supports both legacy and ultra-high speed II (UHS-II) interfaces.
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UHS2 Host Phy
- SD Specifications Part 1 UHS-II Specification Volume 2: PHY Draft Version 0.9
- SD Specifications Part 1 UHS-II Specification Volume 1: System and Protocol Draft Version 0.91
- (Will be SD4.0 Version1.0 compliance when the standard is released)
- Bi-directional receiver/transmitter (2ch) supporting both Full Duplex and Half Duplex modes
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UHS2 Device Phy
- SD Specifications Part 1 UHS-II Specification Volume 2: PHY Draft Version 0.9
- SD Specifications Part 1 UHS-II Specification Volume 1: System and Protocol Draft Version 0.91
- (Will be SD4.0 Version1.0 compliance when the standard is released)
- Bi-directional receiver/transmitter (2ch) supporting both Full Duplex and Half Duplex modes
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UHS-II Device Controller
- Compliance with Part 1 UHS-II Addendum Version 1.02
- Compliance with Part A2 SD Host controller specification version 4.10 & Part1 Physical layer specification version 4.20
- Programmable 1 or 2 Data lane Configuration
- Supports all type of packets
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SD 4.1 Device Controller IP
- Fully compliant core with proven silicon
- Compliant with SD Specification Part E SD Specification 4.0
- Transfers up to 300 MB/s (UHS156)
- Supports Asynchronous Interrupt to Host controller
- Enhanced power management using new Power
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SD 4.1 eMMC 5.1 Dual Host Controller IP
- The SD 4.1/SDIO 4.0/eMMC 5.0 Host IP from Arasan Chip Systems is a highly integrated host controller IP solution that supports three key memory card I/O technologies:
- The SD 4.1 / eMMC 5.1 Host IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds. The IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead. In addition, a host can utilize this IP to boot directly from an attached eMMC memory, thereby simplifying system initialization during power up. The host interface is based on a standard 32-bit AHB bus which is used to transfer data and configure the SD 4.1 / eMMC5.1 Host IP.
- eMMC 5.1 is backward compatible to the previous versions.
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SD 4.1 Hardware Validation Platform
- Designed to be cost-effective and Linux based, this SD 4.1 hardware validation platform (HVP) consists of Arasan’s SD4.0 IP mapped into FPGA’s, offering full speed physical connectivity to a complementary SoC host or memory card device.
