UHS2 Host Phy
Overview
This UHS2PHY IP solution for UHS-II interface that SD Association is working on the standardization as the new ultra high speed interface for both SDHC and SDXC. By using this unique SerDes technology, the UHS2PHY achieves 300MB/s that is the maximum speed for UHS-II with the low power consumption. This PHY IP can be applied to both the device and host sides including SDIO and hence it can be utilized for SOCs for various applications including SD cards, digital cameras, digital videos, digital TVs, media players and personal computers.
Key Features
- SD Specifications Part 1 UHS-II Specification Volume 2: PHY Draft Version 0.9
- SD Specifications Part 1 UHS-II Specification Volume 1: System and Protocol Draft Version 0.91
- (Will be SD4.0 Version1.0 compliance when the standard is released)
- Bi-directional receiver/transmitter (2ch) supporting both Full Duplex and Half Duplex modes
- 390Mbps to 1.56Gbps/ch (Upper Range: 780Mbps ~ 1.56Gbps, Lower Range: 390Mbps ~ 780Mbps)
- RCLK frequency: 26~56MHz
- Power Supply Voltage: 1.0V/3.3V
- Operating Temperature (Tj): -40degreeC ~ 125degreeC
- Clock Recovery
- PLL
- 8B10B
- BIST
- On-chip termination resistors
- Link parallel interface selectable between 8b or 16b
- Programmable PHY parameters
- Silicon Proven in multipl Fab/Nodes
Block Diagram
