UFS 4.0 IP
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11
IP
from 3 vendors
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10)
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UFSHCI 4.0 - UFS Host Controller Interface
- Compliant with JEDEC UFSHCI Standard version 4.0 specification
- Compliant with JEDEC UFS Standard version 4.0 specification
- Up to 32 doorbells for UTP transfers
- Up to 32 Multi-Circular Queue (MCQ) UTP transfer requests
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UFS 4.0 Host Controller compatible with M-PHY 5.0 and UniPro 2.0
- JEDEC UFS 4.0, JEDEC UFS-HCI 4.0, MIPI M-PHY 5.0, MIPI UniPro 2.0
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UFS 3.0 Host Controller compatible with M-PHY 4.0 and UniPro 1.8
- UFS 3.0 Host and Device configurations available
- Complete UFS 3.0 hardware implementation
- Interop-proven UniPro 1.8 link layer
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UFS 3.0 Host Controller with AES Encryption compatible with M-PHY 4.0 and UniPro 1.8
- UFS 3.0 Host and Device configurations available
- Complete UFS 3.0 hardware implementation
- Interop-proven UniPro 1.8 link layer
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UFS Host 3.0 Prototyping Kit (HDK )Total IP in a Box
- UFS 3.0 Host and Device configurations available
- Complete UFS 3.0 hardware implementation
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MIPI M-PHY v4.1 IP, Silicon Proven in TSMC 40 LP
- Compatible with PCIe base Specification
- Full compatible with PIPE3.0 interface specification
- Independent channel power down control
- Implemented Receiver equalization Adaptive-CTLE to compensate insertion loss
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MIPI M-PHY v3.1 IP, Silicon Proven in UMC 40LP
- Compliant with M-PHY Spec 4.1, UniPro Spec 1.8, UFS Spec 3.0
- Support HS-MODE Gear4(A/B) with data rate up to 11.6Gb/s, and backward compatible
- Support LS-MODE PWM-G1 to PWM-G5 with data rate up to 144Mb/s
- Support reference clock frequency with 19.2/26/38.4/52MHz defined in UFS spec.
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MIPI M-PHY - TSMC 40nm
- Compliant to MIPI Alliance Standard for M-PHY specification Version 3.0
- •Supports high speed data transfer G1A/B, G2A/B and G3A/B with data rates of up to 5830.4 Mbps
- •Supports M-PHY Type-I system
- •Support for reference clock frequencies of 19.2MHz/26MHz/38.4MHz/52MHz
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MIPI MPHY v3.1, 1Tx-1Rx Type-1, SMIC 40LL, N/S orientation
- Supports RMMI interface for applications such as UNIPRO protocol (UFS, CSI-3, DSI-2) and DigRF
- High speed gears, HS-G1A/B, HS-G2A/B and HS-G3A/B with scalable power consumptions
- Burst mode CDR with short sync length (< 16SI)
- Low speed PWM Gears from G1 to G4 with ultra-low power consumptions
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MIPI M-PHY v3.1 IP in TSMC(12/16nm, 28nm, 40nm, and 55nm)
- Supports RMMI interface for applications such as UNIPRO protocol (UFS, CSI-3, DSI-2) and DigRF
- High speed gears, HS-G1A/B, HS-G2A/B and HS-G3A/B with scalable power consumptions
- Burst mode CDR with short sync length (< 16SI)
- Low speed PWM Gears from G1 to G4 with ultra-low power consumptions