UFSHCI 4.0 - UFS Host Controller Interface

Overview

The UFS Host Controller Interface (UFSHCI) is a high-performance interface that connects to UniPro and M-PHY IP in mobile platforms. It provides command sets and device management functions for UFS host applications, as well as manages data transfer between the host SW and UFS devices.

The UFSHCI IP is compliant with JEDEC UFSHCI 4.0 specification, which includes the Multi-Circular Queue (MCQ) feature and support for 2DW PRDT to enhance host performance. The UFSHCI IP also provides the AES-128 engine (optional) to meet customers’ security demands.

The UFSHCI IP can be combined with UniPro IP and M-PHY IP to provide a comprehensive UFS host solution, enabling customers to easily integrate it into their applications and accelerate the time-to-market for SoC designs.

Key Features

  • Compliant with JEDEC UFSHCI Standard version 4.0 specification
  • Compliant with JEDEC UFS Standard version 4.0 specification
  • Up to 32 doorbells for UTP transfers
  • Up to 32 Multi-Circular Queue (MCQ) UTP transfer requests
  • 4 sets of multi RTTs
  • Out-of-order data transfer
  • 4DW/2DW PRDT formats
  • PRDT caching supports 32 sets of commands
  • DATAIN and RTT UPIU with Hint field
  • Extended initiator ID (EXT_IID)
  • Power domain partitioning for power saving
  • Auto-hibernate
  • Optional Crypto function for data transfer (AES-XTS 128)
  • 128-bit AXI master interface for data transfer
  • AXI burst length of 1 to 16 transfers

Block Diagram

UFSHCI 4.0 - UFS Host Controller Interface Block Diagram

Technical Specifications

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Semiconductor IP