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UCIe Controller IP

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Compare 41 IP from 6 vendors (1 - 10)
  • UCIe Controller baseline for Streaming Protocols
    • Low latency controller for UCIe-based multi-die designs
    • Includes Die-to-Die Adapter layer and Protocol layer
    • Supports on-chip interconnect fabrics including AXI, CHI C2C, CXS, PCIe, CXL, and streaming
    • Error detection and correction with optional CRC and retry functionality
    Block Diagram -- UCIe Controller baseline for Streaming Protocols
  • UCIe Die-to-Die Controller IP
    • High Configurability and Customizability
    • Comprehensive Verification
    Block Diagram -- UCIe Die-to-Die Controller IP
  • UCIe Die-to-Die Chiplet Controller
    • High configurability and customizability
    • Defines packets to communicate with a link partner using different AXI parameters
    • Supports raw streaming modes
    • Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
    Block Diagram -- UCIe Die-to-Die Chiplet Controller
  • IPTD2D-A PHY and Controller
    • Supports CoWoSTM, INFOTM and EMIBTM package technologies
    • Supports any speed ranging from 2Gbps to 16Gbps, achieving the best balance between total bandwidth and power consumption
  • UCIe-S PHY and Controller
    • Supports MCM, BGA packages and Chiplet2Chiplet interconnects on PCB
    • Available process nodes: 28, 22, 16, 12, 7, 6nm
    • X16 and X32 PHY with bump maps defined in UCIe 2.0 specifications
    • Industry leading power consumption
  • UCIe based 8-bit 48-Gsps Transceiver (ADC/DAC/PLL/UCIe)
    • 48-Gsps peak sample rate
    • 8 bit resolution
    • UCIe SP (16x lanes at 16Gbps) with streaming controller
  • UCIe based 12-bit 12-Gsps Transceiver (ADC/DAC/PLL/UCIe)
    • 12-Gsps peak sample rate
    • 12 bit resolution (programmable)
    • UCIe SP (16x lanes at 16Gbps) with streaming controller
  • UCIe IP Solutions
    • Low Latency controller for UCIe-based die-to-die connectivity
    • Includes Die-to-Die Adapter layer and Protocol layer
    • Supports streaming, CXL and PCI Express protocols
    • Error detection and correction with optional CRC and retry functionality
  • 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
    • High Bandwidth Density and Data Rates
    • Package Configurability
    • Energy Efficiency
    • Fully Integrated Solution
    Block Diagram -- 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
  • TSMC N3P Source Sync 3DIO PHY
    • Optimized for heterogeneous integration in 3D stacking
    • Enabling designers the flexibility and scalability to accelerate multi-die integration
    • Optimal PPA architected to supporting 2.5D and 3D packages
    • Versatile offering tuned for optimal use scenarios, including:
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Semiconductor IP