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TSMC N5 IP

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Compare 156 IP from 6 vendors (1 - 10)
  • USB 2.0 femtoPHY - TSMC N5 12 x1, North/South (vertical) poly orientation
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 femtoPHY - TSMC N5 12 x1, North/South (vertical) poly orientation
  • eUSB 2.0 PHY - TSMC N5 x1, North/South (vertical) poly orientation
    • Designed for 7nm processes and below
    • Supports the USB 2.0 protocol and High Speed, Full Speed, and Low Speed data rates
    • eUSB2 PHYs supports USB 2.0, 3.0, 3.1 and 3.2 Device, Host and Dual Role configurations
    Block Diagram -- eUSB 2.0 PHY - TSMC N5 x1, North/South (vertical) poly orientation
  • USB-C 3.2 DP/TX PHY ebdaux for TSMC N5, North/South poly orientation
    • USB-IF certified Synopsys USB 3.2 solution
    • VESA certified Synopsys DisplayPort 1.4 Tx solution
    • Industry’s only USB Type-C IP solution consisting of USB-C 3.2/DisplayPort 1.4 TX PHYs, USB-C 3.2/DisplayPort 1.4 TX controllers with HDCP 2.2 and HDCP 2.2 content protection, verification IP, and IP subsystems
    • Solution supports USB Type-C, SuperSpeed USB 3.2 at 20 Gbps, SuperSpeed USB 3.1 at 10 Gbps, SuperSpeed USB 3.0 at 5 Gbps and High-Speed USB (USB 2.0) as well as DisplayPort 1.4 TX supporting RBR, HBR1, HBR2 and HBR3 bitrates
    Block Diagram -- USB-C 3.2 DP/TX PHY ebdaux for TSMC N5, North/South poly orientation
  • USB-C 3.1 SS/SSP PHY, Type-C - TSMC N5, North/South Poly Orientation
    • Part of a complete IP solution including xHCI host and device controllers, PHYs, verification IP, 1 IP Prototyping Kits and IP software development kits
    • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
    • USB-C 3.1 PHY IP supports USB Type-C specification
    • Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
    Block Diagram -- USB-C 3.1 SS/SSP PHY, Type-C - TSMC N5, North/South Poly Orientation
  • USB 3.1 PHY (10G/5G) - TSMC N5 x1 OTG, North/South Poly Orientation
    • Part of a complete IP solution including xHCI host and device controllers, PHYs, verification IP, 1 IP Prototyping Kits and IP software development kits
    • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
    • USB-C 3.1 PHY IP supports USB Type-C specification
    • Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
    Block Diagram -- USB 3.1 PHY (10G/5G) - TSMC N5 x1 OTG, North/South Poly Orientation
  • USB4 PHY - TSMC N5 1.2V, North/South Poly Orientation
    • Supports 40 Gbps, 20 Gbps, 10 Gbps, and 5 Gbps data rates
    • Supports 480 Mbps, 12 Mbps, and 1.5 Mbps data rates
    • x1 and x2 configurations (USB 3.2 and USB 3.1 PHY only)
    • Low active and standby power
    Block Diagram -- USB4 PHY - TSMC N5 1.2V, North/South Poly Orientation
  • 10G PHY for PCIe 3.0, TSMC N5 X2, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 3.1, 2.1, 1.1 and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
    • L1 substate and SRIS support
    Block Diagram -- 10G PHY for PCIe 3.0, TSMC N5 X2, North/South (vertical) poly orientation
  • 20G PHY for PCIe 4.0, TSMC N5 1.2V x4, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 4.0, 3.1, 2.1, 1.1, and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
    • Supports lane margining at the receiver
    Block Diagram -- 20G PHY for PCIe 4.0, TSMC N5 1.2V x4, North/South (vertical) poly orientation
  • 20G PHY for PCIe 4 PHY, TSMC N5 1.2V x1, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 4.0, 3.1, 2.1, 1.1, and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
    • Supports lane margining at the receiver
    Block Diagram -- 20G PHY for PCIe 4 PHY, TSMC N5 1.2V x1, North/South (vertical) poly orientation
  • PCIe 7.0 PHY, TSMC N5 x4, North/South (vertical) poly orientation
    • Supports the latest features of PCIe® 7.0 specification
    • Supports PAM-4 signaling and up to x16 lane configurations with bifurcation
    • Unique DSP algorithms deliver more power efficiency across channels
    • Patent-pending diagnostic features enable near zero link downtime
    Block Diagram -- PCIe 7.0 PHY, TSMC N5 x4, North/South (vertical) poly orientation
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