SoundWire‑I3S IP

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Compare 3 IP from 3 vendors (1 - 3)
  • Simulation VIP for MIPI SoundWire-I3S
    • PHYs
    • Supports LC PHY and DLV PHY
    • Interfaces
    • Supports serial interface
    Block Diagram -- Simulation VIP for MIPI SoundWire-I3S
  • MIPI SWI3S Manager Core IP
    • The SWI3S (SoundWire I3S Interface) Manager Controller Core IP implements the link protocol to communicate in half-duplex fashion to transfer the Audio streams and the Control information together.
    • One or more SWI3S Peripheral IP can be connected specific to the application.
    Block Diagram -- MIPI SWI3S Manager Core IP
  • MIPI SoundWire I3S Verification IP
    • Full MIPI SoundWire I3S Master, Slave and Monitor functionality
    • Supports MIPI Soundwire-I3S Bus Draft Specification v0.4r06.
    • Supports system with one master and one or more slaves (upto 8 slaves).
    • Supports LVDS PHY for higher speed and a single-ended CMOS PHY for lower speed systems.
    Block Diagram -- MIPI SoundWire I3S Verification IP
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Semiconductor IP