Single port sram IP

Ultra low power data retention. Memory instances generated by the Bulk 40 ULPgo into a deep sleep mode that retains data at minimal power consumption.

Uses low leakage devices and source biasing to minimize standby currents.
Dedicated standy mode with built in source biasing for the memory array.
Periphery and array supplies are isolated to allow power off of the perphery when in standy mode.
.8V supply voltage

Ultra low power data retention. Memory instances generated by the Bulk 22ULL go into a deep sleep mode that retains data at minimal power consumption.
Self biasing. The SP SRAM 22ULL internal self-biasing capabilities provide ease of IP integration.
High yield. To ensure high manufacturing yield, bulk 22ULL uses low leakage 6T (0.110µ2) bit cells and is consistent with Design for Manufacturing (DFM) guidelines for the Bulk 22ULL process.
High usability. All signal and power pins are available on metal 4 while maintaining routing porosity in metal 4. Power pins can optionally be made available on metal 5 to simplify the power connections at the chip level.

Uses low leakage devices and source biasing to minimize standby currents.
Dedicated standy mode with built in source biasing for the memory array.
Periphery and array supplies are isolated to allow power off of the perphery when in standy mode.
.8V supply voltage

The High Density Single Port SRAM operates within voltage range from 0.675 V to 0.825 V and junction temperature range from -40 °C to 125 °C. The available supported macro size is configurable from 512 bits to 576K bits. The Compiler is divided into 1 groups according to their column selection numbers (Mux=8).
? Pins and metal layers
– 1P3M (1X_h_1Xb_v): 3 metal layers used and top metal is MXb.
– Power mesh supported with M3 pins

Foundry Sponsored Memory Instance
Smart periphery design to reach the highest density
Memory designed with SVT MOS for periphery and SVT HD PRBC from TSMC for memory core
Flexible architecture

Smart periphery design to reach the highest density
Memory designed with SVT MOS for periphery and SVT HD PRBC from TSMC for memory core
Flexible architecture
To offer several performance trade-offs for any memory size

Single port SRAM IP