Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k

Overview

Single Port SRAM compiler - TSMC 180 nm BCD Gen2 - Memory optimized for high density and Low power - compiler range up to 320 k

Memory generator
SVT TSMC Bit-cell for memory core and SVT MOS for memory periphery
Migration of a mass produced architecture already available in other geometries(90nm, 55 nm)
Up to 30% denser than competition SRAM
Ultra Low dynamic power
Partitioned array
Variable write-mask capability
Flexible power routing: power ring or ring-less
Low leakage design
Stand by mode
Data retention mode at nominal voltage (1.8 V) and low voltage (1.0 V) for 8x leakage reduction compared to stand by mode
Flexible architecture
To offer several performance trade-offs for any memory size
Multiple form factors proposed by the generator for a given capacity
Easy integration
Data range flexibility allows easy addition of bits for redundancy or ECC purposes
Address range flexibility allows easy addition of single rows for redundancy purposes
The Dolphin quality
Complete mismatch validation of the memory architecture taking into account local and global dispersions
Compliance with TSMC IP 9000 qualification process

Maturity

In_Production